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    System on chip
    1.
    发明授权
    System on chip 有权
    片上系统

    公开(公告)号：US09589955B2

    公开(公告)日：2017-03-07

    申请号：US14872774

    申请日：2015-10-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11

    CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Abstract translation: 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    System on chip
    2.
    发明授权
    System on chip 有权

    公开(公告)号：US10050032B2

    公开(公告)日：2018-08-14

    申请号：US15416016

    申请日：2017-01-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Semiconductor device and method of fabricating the same
    3.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US09640444B2

    公开(公告)日：2017-05-02

    申请号：US14807220

    申请日：2015-07-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jung-Ho Do ,  Sanghoon Baek ,  Sang-Kyu Oh ,  Kwanyoung Chun ,  Sunyoung Park ,  Taejoong Song

    IPC: H01L21/70 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02

    CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

    Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

    System on chip
    6.
    发明授权
    System on chip 有权

    公开(公告)号：US10541237B2

    公开(公告)日：2020-01-21

    申请号：US16037581

    申请日：2018-07-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-Young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/8234 ,  H01L23/528

    Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

    System on chip
    9.
    发明授权
    System on chip 有权

    公开(公告)号：US11201150B2

    公开(公告)日：2021-12-14

    申请号：US16746071

    申请日：2020-01-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Hoon Baek ,  Sun-Young Park ,  Sang-Kyu Oh ,  Ha-young Kim ,  Jung-Ho Do ,  Moo-Gyu Bae ,  Seung-Young Lee

    IPC: H01L23/48 ,  H01L29/40 ,  H01L27/088 ,  H01L27/02 ,  H01L27/11 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L23/528

    Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

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