公开(公告)号：US20220415835A1

公开(公告)日：2022-12-29

申请号：US17742852

申请日：2022-05-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun BAE ,  Seokhyun LEE ,  Eungkyu KIM

IPC: H01L23/00

Abstract: Disclosed are semiconductor packages and their fabricating methods. A semiconductor package includes a semiconductor chip on a redistribution substrate. The redistribution substrate includes a base dielectric layer and upper coupling pads in the base dielectric layer. Top surfaces of the upper coupling pads are coplanar with a top surface of the base dielectric layer. The semiconductor chip includes a redistribution dielectric layer and redistribution chip pads in the redistribution dielectric layer. Top surfaces of the redistribution chip pads are coplanar with a top surface of the redistribution dielectric layer. The top surface of the redistribution dielectric layer is bonded to the top surface of the base dielectric layer. The redistribution chip pads are bonded to the upper coupling pads. The redistribution chip pads and the upper coupling pads include a same metallic material. The redistribution dielectric layer and the base dielectric layer include a photosensitive polymer layer.

公开(公告)号：US20220415802A1

公开(公告)日：2022-12-29

申请号：US17683774

申请日：2022-03-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyu KIM ,  Seokkyu CHOI ,  Minjung KIM ,  Seokhyun LEE

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a redistribution substrate including a first surface and a second surface that are opposite to each other, an antenna substrate on the first surface and including a first insulating portion and antenna patterns on a top surface of the first insulating portion, and a first semiconductor chip on the second surface. The redistribution substrate includes a second insulating portion, and a redistribution pattern in the second insulating portion. The redistribution pattern includes an interconnection portion extending parallel to a top surface of the second insulating portion, and a via portion protruding from the interconnection portion toward the first surface. A width of the via portion decreases as a height in a direction from the second surface toward the first surface increases. The active surface of the first semiconductor chip is adjacent to the second surface.

公开(公告)号：US20220328388A1

公开(公告)日：2022-10-13

申请号：US17508250

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Kyounglim SUK ,  Seokhyun LEE

IPC: H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.

公开(公告)号：US20220077041A1

公开(公告)日：2022-03-10

申请号：US17405603

申请日：2021-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gwangjae JEON ,  Jung-Ho PARK ,  Seokhyun LEE ,  Yaejung YOON

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

公开(公告)号：US20200266136A1

公开(公告)日：2020-08-20

申请号：US16676716

申请日：2019-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokhyun LEE

IPC: H01L23/495 ,  H01L23/532 ,  H01L23/522

Abstract: A redistribution substrate includes a first conductive pattern including a first lower pad and a second lower pad, the first and second lower pads being within a first insulating layer, a second conductive pattern including a first upper pad and a second upper pad, the first and second upper pads being on the first insulating layer, a first via connecting the first lower pad and the first upper pad to each other in the first insulating layer, a second via connecting the second lower pad and the second upper pad to each other in the first insulating layer, and a capacitor between the first lower pad and the first via.

公开(公告)号：US20200091066A1

公开(公告)日：2020-03-19

申请号：US16351709

申请日：2019-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongyoun KIM ,  Seokhyun LEE ,  Minjun BAE

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.

公开(公告)号：US20230069490A1

公开(公告)日：2023-03-02

申请号：US17723981

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonseok LEE ,  Jongyoun KIM ,  Seokhyun LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces, a first semiconductor chip on the first surface, external terminals on the second surface, a second semiconductor chip above the first semiconductor chip, external connection members below the second semiconductor chip, conductive pillars electrically connecting the external connection members to the redistribution substrate. The second semiconductor chip includes a device layer, a wiring layer, and a redistribution layer on a semiconductor substrate. The wiring layer includes intermetallic dielectric layers, wiring lines, and a conductive pad connected to an uppermost wiring line. The redistribution layer includes a first redistribution dielectric layer, a first redistribution pattern, and a second redistribution dielectric layer. A vertical distance between the semiconductor substrate and the conductive pillars is less than that between the first semiconductor chip and the external terminals.

公开(公告)号：US20220367403A1

公开(公告)日：2022-11-17

申请号：US17711359

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Dongkyu KIM ,  Kyounglim SUK ,  Hyeonjeong HWANG

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.

公开(公告)号：US20220367402A1

公开(公告)日：2022-11-17

申请号：US17648425

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd

Inventor： INHYUNG SONG ,  Seokhyun LEE ,  Jongyoun KIM

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor package includes a base substrate; a redistribution substrate disposed on the base substrate, and that includes first insulating layers and redistribution pattern layers disposed on the first insulating layers, respectively; a semiconductor chip disposed on the redistribution substrate and electrically connected to the redistribution pattern layers; and a chip structure disposed on the redistribution substrate adjacent to the semiconductor chip and electrically connected to the semiconductor chip through the redistribution pattern layers, wherein the semiconductor chip includes a body that has an active surface that faces the redistribution substrate; first and second contact pads spaced apart from each other below the active surface; a first bump structure and a passive device electrically connected to the first connection pad at a lower level from the first connection pad; and a second bump structure electrically connected to the second connection pad at a lower level from the second connection pad.

公开(公告)号：US20210111114A1

公开(公告)日：2021-04-15

申请号：US16884212

申请日：2020-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokhyun LEE ,  Jongyoun KIM ,  Yeonho JANG ,  Jaegwon JANG

IPC: H01L23/498 ,  H01L21/48

Abstract: A semiconductor package includes a semiconductor chip, a redistribution structure below the semiconductor chip, a first insulating layer below the redistribution structure, a pad below the first insulating layer, the pad being in contact with the redistribution structure, and a bump below the pad, wherein a horizontal maximum length of an upper portion of the pad is greater than a horizontal maximum length of a lower portion of the pad.