公开(公告)号：US12231528B2

公开(公告)日：2025-02-18

申请号：US18197079

申请日：2023-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongmo Moon ,  Jeonghyeok You ,  Seongook Jung ,  Taeryeong Kim ,  Hohyun Chae

IPC: H04L7/00 ,  G06F1/04 ,  H03K3/017 ,  H03K3/037 ,  H03K5/14 ,  H03K5/00 ,  H03K19/20

Abstract: An apparatus for correcting an error of a clock signal may include a phase adjuster that corrects an error of half-rate clock signals based on an error correction signal to output an error-corrected clock signal, a phase splitter that outputs quadrature clock signals from the error-corrected clock signal, an error detector that outputs an internal clock signal based on one of the quadrature clock signals, selects two quadrature clock signals among the quadrature clock signals based on a clock selection signal, and detects errors of the two quadrature clock signals based on an error check signal to output a correction request signal, and a controller that outputs a mode selection signal and the clock selection signal based on the internal clock signal and that outputs the error correction signal and the error check signal based on the mode selection signal, the clock selection signal, and the correction request signal.

公开(公告)号：US20240233812A1

公开(公告)日：2024-07-11

申请号：US18227355

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjun KIM ,  Sekeon Kim ,  Seongook Jung ,  Kyeongrim Baek ,  Keonhee Cho

IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4074

Abstract: A memory cell array of an SRAM including: a top memory cell array including top memory cells; and a bottom memory cell array including bottom memory cells, the top memory cells include: a first top memory cell between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, the bottom memory cells include: a first bottom memory cell to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when write and read operations are not performed on the first top and bottom memory cells, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are connected to the middle node.

公开(公告)号：US11670360B2

公开(公告)日：2023-06-06

申请号：US17335606

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/4074 ,  G11C5/06

CPC classification number: G11C11/4085 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4099

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.

公开(公告)号：US20220139442A1

公开(公告)日：2022-05-05

申请号：US17335606

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Choi ,  Seongook Jung ,  Keonhee Cho

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/06

Abstract: An integrated circuit includes: a cell array including a plurality of memory cells in a plurality of first columns and including a plurality of word line assist cells in at least one second column; a plurality of word lines respectively extending on a plurality of first rows of the cell array and connected to the plurality of memory cells and the plurality of word line assist cells; and a row driver configured to drive the plurality of word lines.