公开(公告)号：US20250068938A1

公开(公告)日：2025-02-27

申请号：US18426830

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Minje KIM ,  Jaejin LEE ,  Dohun KIM ,  Jinpyo KIM ,  Soon-Wan KWON ,  Heehoon KIM ,  Daeyoung PARK

IPC: G06N5/022 ,  G06F1/3203 ,  G06N3/04

Abstract: A processor-implemented method includes obtaining a benchmark execution result, receiving input data comprising a neural network model subject to prediction and analysis requirement information, receiving information on hardware of a device in which the neural network model is run, building a prediction model based on the benchmark execution result and the hardware information, extracting layer information respectively corresponding to a plurality of layers configuring the neural network model, and predicting either one or both of operation performance information and energy efficiency information respectively corresponding to the plurality of layers by inputting the analysis requirement information and the layer information to the prediction model.

公开(公告)号：US20240249110A1

公开(公告)日：2024-07-25

申请号：US18344201

申请日：2023-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minje KIM ,  Soon-Wan KWON ,  Wooseok YI ,  Jangho AN

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: A device includes: an operation module configured to store and operate a weight for an operation of a layer of a neural network model; a control module configured to generate setting information for performing the operation of the layer by the neural network model using the stored weight; an input module configured to receive input data for the operation of the layer based on the generated setting information; a merging module configured to receive operation results of the operation of the layer from the operation module and merge the received operation results of the layer; a post-processing module configured to receive the merged operation results of the layer from the merging module and post-process the received merged operation results of the layer; and an output stream module configured to convert and store the post-processed operation results based on the generated setting information.

公开(公告)号：US20240231757A9

公开(公告)日：2024-07-11

申请号：US18322837

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok YI ,  Soon-Wan KWON ,  Seungchul JUNG

IPC: G06F7/544 ,  G06F7/556

CPC classification number: G06F7/5443 ,  G06F7/556

Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

公开(公告)号：US20240134606A1

公开(公告)日：2024-04-25

申请号：US18322837

申请日：2023-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wooseok YI ,  Soon-Wan KWON ,  Seungchul JUNG

IPC: G06F7/544 ,  G06F7/556

CPC classification number: G06F7/5443 ,  G06F7/556

Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

公开(公告)号：US20240103809A1

公开(公告)日：2024-03-28

申请号：US18139567

申请日：2023-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jin CHANG ,  Soon-Wan KWON ,  Seok Ju YUN ,  Jaehyuk LEE ,  Sungmeen MYUNG ,  Daekun YOON

IPC: G06F7/507 ,  G06F7/504 ,  G06F7/544

CPC classification number: G06F7/507 ,  G06F7/504 ,  G06F7/5443

Abstract: Provided is a computation method of a memory processor configured to perform an operation between a first vector including first elements and a second vector including second elements, the first elements including respective first bits and the second elements including respective second bits, the method performed by the memory processor including: applying, to single-bit operation gates, the respective first bits and the respective second bits; obtaining bit operation result sum values for the respective first and second elements based on bit operation results obtained using the single-bit operation gates; and obtaining an operation result of the first vector and the second vector based on the bit operation result sum value.

公开(公告)号：US20190205169A1

公开(公告)日：2019-07-04

申请号：US15774173

申请日：2016-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Beom LEE ,  Ahmed ALIF ,  Joongbaik KIM ,  Soon-Wan KWON

IPC: G06F9/48 ,  H04L29/08 ,  G06F9/50

CPC classification number: G06F9/4887 ,  G06F9/5038 ,  G06F13/10 ,  G06F13/1642 ,  G06F13/18 ,  G06F13/22 ,  G06F13/362 ,  G06F13/38 ,  G06F13/40 ,  H04L67/025

Abstract: A device according to various embodiments may comprise: a transceiver unit configured to transmit or receive information; and a control unit operatively coupled to the transceiver unit, wherein the control unit may be configured to receive, from each of a plurality of control devices that transmit a request for data to a storage device, state information of each of the plurality of control devices, to determine a threshold value for an outstanding data request of each of the plurality of control devices on the basis of the received state information, and to transmit the threshold value to at least one other device.