公开(公告)号：US10236045B2

公开(公告)日：2019-03-19

申请号：US13828869

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C7/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C8/00 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US20200168259A1

公开(公告)日：2020-05-28

申请号：US16778431

申请日：2020-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/18 ,  G06F11/10 ,  G11C11/4076 ,  G11C7/22 ,  G11C5/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10593387B2

公开(公告)日：2020-03-17

申请号：US16274860

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G11C5/04 ,  G11C7/22 ,  G11C11/4076 ,  G06F11/10 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US20190180795A1

公开(公告)日：2019-06-13

申请号：US16275396

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G11C5/14 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3287

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US20170294216A1

公开(公告)日：2017-10-12

申请号：US15416140

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G11C5/14 ,  G06F1/26 ,  G06F1/32

CPC classification number: G11C5/148 ,  G06F1/266 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US09607678B2

公开(公告)日：2017-03-28

申请号：US14959003

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Young Oh ,  Su Yeon Doo ,  Seung Hoon Oh ,  Jong Ho Lee ,  Kwang Il Park

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40618

Abstract: A method of operating a semiconductor memory device is provided as follows. The semiconductor memory device receive a bank address for a first bank including a first word line, a second word line and a third word line. The semiconductor memory device receive a first row address to activate the first world line for a read operation or a write operation. The semiconductor memory device generates a second row address to refresh a plurality of memory cells associated with the second word line.