公开(公告)号：US10223311B2

公开(公告)日：2019-03-05

申请号：US14976865

申请日：2015-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Tae Young Oh

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/40 ,  G06F13/362

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

公开(公告)号：US11087822B2

公开(公告)日：2021-08-10

申请号：US17093786

申请日：2020-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10726882B2

公开(公告)日：2020-07-28

申请号：US16275396

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G06F1/00 ,  G11C5/14 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/26 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.

公开(公告)号：US10255964B2

公开(公告)日：2019-04-09

申请号：US15081071

申请日：2016-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US11621034B2

公开(公告)日：2023-04-04

申请号：US17376915

申请日：2021-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10699770B2

公开(公告)日：2020-06-30

申请号：US16579994

申请日：2019-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C7/10 ,  G11C8/18

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10460793B2

公开(公告)日：2019-10-29

申请号：US16278339

申请日：2019-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungjun Shin ,  Su Yeon Doo ,  Taeyoung Oh

IPC: G11C11/00 ,  G11C8/10 ,  G11C11/4076 ,  G11C8/18 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/408

Abstract: A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.

公开(公告)号：US10777246B2

公开(公告)日：2020-09-15

申请号：US16778431

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Seungjun Bae ,  Sihong Kim ,  Hosung Song

IPC: G11C8/00 ,  G11C8/18 ,  G06F11/10 ,  G11C7/22 ,  G11C5/04 ,  G11C11/4076 ,  G11C29/04

Abstract: A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.

公开(公告)号：US10719467B2

公开(公告)日：2020-07-21

申请号：US16250290

申请日：2019-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Su Yeon Doo ,  Tae Young Oh

IPC: G06F13/36 ,  G06F13/16 ,  G06F13/40 ,  G06F13/362 ,  G06F13/42

Abstract: A method of operating a memory controller, memory devices including a master memory device and slave memory devices, a back channel bus coupling the master memory device to the slave memory devices and a channel coupling the memory controller to the memory devices is provided as follows. A memory command is received by the memory devices from the memory controller. An internal command is generated and outputted by the master memory device. The internal command is received by the slave memory devices. The internal command is transmitted to the slave memory devices through the back channel bus.

公开(公告)号：US10242719B2

公开(公告)日：2019-03-26

申请号：US15416140

申请日：2017-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su Yeon Doo ,  Taeyoung Oh

IPC: G06F1/00 ,  G11C5/14 ,  G06F1/26 ,  G06F1/3287 ,  G06F1/3296

Abstract: An electronic device includes a memory device including a power switch configured to provide one of a first voltage and a second voltage to an internal circuit in response to a control command. A power management device is configured to generate the first voltage, the second voltage, and the control command and to provide the first voltage, the second voltage, and the control command to the memory device. The power switch provides the second voltage to the internal circuit while a level of the first voltage is changed and provides the first voltage to the internal circuit after a level change of the first voltage is completed.