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公开(公告)号：US10734043B2
公开(公告)日：2020-08-04
申请号：US16054633
申请日：2018-08-03
发明人： Young-Ju Kim , Dong-Seok Kang , Hye Jung Kwon , Byungchul Kim , Seungjun Bae
IPC分类号： G11C8/00 , G11C7/10 , H03L7/08 , G11C8/18 , G11C11/408 , G11C11/4096 , G11C11/4076 , G11C29/02 , G11C7/22 , G11C7/02 , G06F13/42 , G11C11/4093 , G06F13/16
摘要： A memory system includes a logic circuit and a phase locked loop (PLL) circuit. The logic circuit determines a first frequency of a first clock using a first signal and generates a second signal for adjusting the first frequency of the first clock. The PLL circuit receives a second clock, and generates the first clock having the first frequency determined by the logic circuit, using the second clock and the second signal. When a second frequency of the second clock varies, the logic circuit determines the first frequency of the first clock such that the first frequency of the first clock generated by the PLL circuit is uniform, and operates based on the first clock having the first frequency adjusted by the second signal.
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公开(公告)号：US10692561B2
公开(公告)日：2020-06-23
申请号：US16032361
申请日：2018-07-11
发明人： Min-soo Jang , Eunsung Seo , Seungjun Bae
IPC分类号： G11C11/40 , G11C11/406 , G11C7/10 , G11C11/408 , H04N5/335
摘要： A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.
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公开(公告)号：US10666467B2
公开(公告)日：2020-05-26
申请号：US16108894
申请日：2018-08-22
发明人： Hye Jung Kwon , Seungjun Bae , Yongjae Lee , Young-Sik Kim , Young-Ju Kim , Suyeon Doo , Yoon-Joo Eom
摘要： A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
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公开(公告)号：US10777246B2
公开(公告)日：2020-09-15
申请号：US16778431
申请日：2020-01-31
发明人： Su Yeon Doo , Seungjun Bae , Sihong Kim , Hosung Song
摘要： A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
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公开(公告)号：US10236045B2
公开(公告)日：2019-03-19
申请号：US13828869
申请日：2013-03-14
发明人： Su Yeon Doo , Seungjun Bae , Sihong Kim , Hosung Song
摘要： A clock pattern generating method of a semiconductor memory device is provided. The method includes generating the same clock pattern through a plurality of detection clock output pins when an output selection control signal is in a first state and generating clock patterns different from each other through the plurality of detection clock output pins when the output selection control signal is in a second state different from the first state.
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公开(公告)号：US09355706B2
公开(公告)日：2016-05-31
申请号：US14322129
申请日：2014-07-02
发明人： Minsu Ahn , Seungjun Bae , Joon-Young Park , Yoon-Joo Eom
IPC分类号： G11C7/10 , G11C11/4076 , G11C7/02 , G11C7/22 , G11C11/4093
CPC分类号： G11C11/4076 , G11C7/02 , G11C7/1066 , G11C7/222 , G11C11/4093
摘要： An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.
摘要翻译： 输出电路包括第一和第二输出驱动器。 第一输出驱动器被配置为与时钟信号同步地将第一数据信号直接传送到输出焊盘。 第二输出驱动器被配置为与反相时钟信号同步地将第二数据信号直接传送到输出焊盘。 时钟信号和反相时钟使第一数据信号和第二数据信号复用，从而提供多路输出数据信号。
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公开(公告)号：US20190158320A1
公开(公告)日：2019-05-23
申请号：US16108894
申请日：2018-08-22
发明人： Hye Jung Kwon , Seungjun Bae , Yongjae Lee , Young-Sik Kim , Young-Ju Kim , Suyeon Doo , Yoon-Joo Eom
摘要： A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.
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公开(公告)号：US11862234B2
公开(公告)日：2024-01-02
申请号：US17457077
申请日：2021-12-01
发明人： Yoon-Joo Eom , Seungjun Bae , Hye Jung Kwon , Young-Ju Kim
IPC分类号： G11C7/20 , G11C11/4093 , G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C11/4096 , G11C7/14 , G11C7/02 , G11C29/50 , G11C11/4072 , G11C29/02 , G11C7/10 , G11C5/14
CPC分类号： G11C11/4093 , G11C5/147 , G11C7/02 , G11C7/1069 , G11C7/14 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C11/4087 , G11C11/4091 , G11C11/4096 , G11C29/028 , G11C29/50 , G11C29/021 , G11C29/023 , G11C2207/2254
摘要： A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
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公开(公告)号：US11195571B2
公开(公告)日：2021-12-07
申请号：US16136895
申请日：2018-09-20
发明人： Yoon-Joo Eom , Seungjun Bae , Hye Jung Kwon , Young-Ju Kim
IPC分类号： G11C11/4093 , G11C11/4091 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C11/4096 , G11C7/14 , G11C7/20 , G11C7/02 , G11C29/50 , G11C11/4072 , G11C29/02 , G11C7/10 , G11C5/14
摘要： A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.
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公开(公告)号：US11056158B2
公开(公告)日：2021-07-06
申请号：US16571868
申请日：2019-09-16
发明人： Dong-Seok Kang , Seungjun Bae
IPC分类号： G11C7/10 , G06F3/06 , H03L7/091 , H03L7/081 , G11C29/02 , H03L7/08 , H04L7/10 , H04L7/033 , G11C7/22 , H03L7/085 , H04L7/00 , H04L7/08 , H04L25/02
摘要： A memory device includes an internal clock generator, a deserializer, a data comparator, and a clock controller. The internal clock generator generates a plurality of internal clock signals, which have different phases from each other, by dividing a clock signal received from a host. The deserializer deserializes serial test data received from a host as pieces of internal data using the internal clock signals. The data comparator compares reference data with the internal data. The clock controller corrects a clock dividing start time point of the clock signal of the internal clock generator based on the result of the comparison of the reference data and the internal data.
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