公开(公告)号：US20230307423A1

公开(公告)日：2023-09-28

申请号：US18328389

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L23/481 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06593 ,  H01L2224/08145

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US20200066683A1

公开(公告)日：2020-02-27

申请号：US16508857

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US20190221439A1

公开(公告)日：2019-07-18

申请号：US16051683

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dong Won KIM

IPC: H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

Abstract: A method including forming hard mask patterns on a substrate; forming etch stop patterns surrounding the hard mask patterns; forming spacer patterns covering sidewalls of the etch stop patterns; removing the etch stop patterns; etching the substrate to form active and dummy fins; forming a block mask pattern layer surrounding the active and dummy fins and forming mask etch patterns on a top surface of the block mask pattern layer; etching the block mask pattern layer to form block mask patterns surrounding the active fins; etching the dummy fins; removing the block mask patterns surrounding the active fins; and depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins, wherein a spacing distance between the active fin and the dummy fin is greater than an active fin spacing distance between the active fins.

公开(公告)号：US20250022876A1

公开(公告)日：2025-01-16

申请号：US18901283

申请日：2024-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/528 ,  H01L27/088 ,  H01L27/146 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

公开(公告)号：US20220254650A1

公开(公告)日：2022-08-11

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young CHOI ,  Sung Min KIM ,  Cheol KIM ,  Hyo Jin KIM ,  Dae Won HA ,  Dong Woo HAN

IPC: H01L21/3213 ,  H01L21/308

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

公开(公告)号：US20220077292A1

公开(公告)日：2022-03-10

申请号：US17227848

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deok Han BAE ,  Sung Min KIM ,  Ju Hun PARK ,  Myung Yoon UM ,  Jong Mil YOUN

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.

公开(公告)号：US20190312032A1

公开(公告)日：2019-10-10

申请号：US16372534

申请日：2019-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dong Won KIM

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device is provided, which includes a first and second multichannel active patterns spaced apart from one another and extending in a first direction. The semiconductor device also includes first and second gate structures on the first and second multichannel active patterns, extending in a second direction and including first and second gate insulating films, respectively. Sidewalls of the first multichannel active pattern include first portions in contact with the first gate insulating film, second portions not in contact with the first gate insulating film, third portions in contact with the second gate insulating film, and fourth portions not in contact with the second gate insulating film. Additionally, a height of the first portions of the first multichannel active pattern is greater than a height of the third portions of the first multichannel active pattern.