公开(公告)号：US20220310654A1

公开(公告)日：2022-09-29

申请号：US17502380

申请日：2021-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Do Young CHOI ,  Kab Jin NAM ,  In Bong POK ,  Dae Won HA ,  Musarrat HASAN

IPC: H01L27/11592 ,  H01L27/1159 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

公开(公告)号：US20240145560A1

公开(公告)日：2024-05-02

申请号：US18211786

申请日：2023-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Hoon HWANG ,  Myung Il KANG ,  Do Young CHOI

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41775 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate extending in a first horizontal direction, a gate electrode on the active pattern extending in a second horizontal direction, a source/drain region on the active pattern, an upper source/drain region apart from the lower source/drain region, a lower source/drain between upper and lower source/drain regions and connected to the lower source/drain region, an upper source/drain connected to an upper source/drain region, an interlayer insulating layer surrounding the upper source/drain region, a through-via on opposing sidewalls in the second horizontal direction extending through the interlayer insulating layer in the vertical direction, the through-via being spaced from the upper source/drain region and upper source/drain contact in the second horizontal direction, the through-via being connected to the lower source/drain contact, and a dam structure on each of the opposing sidewalls in the horizontal direction of the upper source/drain region.

公开(公告)号：US20230352523A1

公开(公告)日：2023-11-02

申请号：US18079537

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Min SONG ,  Myung Il KANG ,  Do Young CHOI

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0649 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, an active pattern on the substrate, a plurality of lower nanosheets stacked on the active pattern, a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including first to third layers sequentially stacked on each other, a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked on the separation structure, and a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each of the plurality of lower nanosheets, and each of the plurality of upper nanosheets. The first and third layers include the same material, and each of the first layer and the third layer includes a material different from a material of the second layer.

公开(公告)号：US20240145474A1

公开(公告)日：2024-05-02

申请号：US18314484

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung ho KIM ,  Myung Il KANG ,  Sung Uk JANG ,  Kyung Hee CHO ,  Do Young CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.

公开(公告)号：US20220254650A1

公开(公告)日：2022-08-11

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young CHOI ,  Sung Min KIM ,  Cheol KIM ,  Hyo Jin KIM ,  Dae Won HA ,  Dong Woo HAN

IPC: H01L21/3213 ,  H01L21/308

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.