-
11.发明授权公开(公告)号：US12113545B2
公开(公告)日：2024-10-08
申请号：US17872173
申请日：2022-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yanghoon Lee , Wan Kim
Abstract: A capacitor digital-to-analog converter (CDAC) includes a clock generator, a random reset control signal generator, a first capacitor array, a first reset circuit and an output buffer. The clock generator generates an internal clock signal and a reset control signal that are regularly toggled. The random reset control signal generator generates a random reset control signal that is irregularly toggled. The first capacitor array includes a plurality of capacitors connected to a first summation node, and generates a first summation voltage corresponding to a first input digital signal based on first and second reference voltages. The first reset circuit initializes the first summation node based on the random reset control signal. The output buffer generates a first analog output voltage by buffering the first summation voltage.
-
Patent Agency Ranking
12.发明授权公开(公告)号：US11870471B2
公开(公告)日：2024-01-09
申请号：US18151711
申请日：2023-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngsea Cho , Jiseon Paek , Wan Kim , Daechul Jeong
CPC classification number: H04B1/0017 , H04B1/1676 , H04B1/62
Abstract: A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.
-
13.发明公开公开(公告)号：US20230269125A1
公开(公告)日：2023-08-24
申请号：US18168320
申请日：2023-02-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dong Han KIM , Sung Soo Kim , Wan Kim
CPC classification number: H04L27/3863 , H03K5/01 , H03K2005/00286
Abstract: An electronic device includes a feedback oscillator configured to output a first oscillation signal and a second oscillation signal, the second oscillation signal having a defined phase difference from the first oscillation signal, the feedback oscillator including a phase shifter configured to receive the first oscillation signal and output the second oscillation signal, an up-conversion mixer configured to output a first loopback signal obtained by mixing the first oscillation signal with a reference tone signal, and output a second loopback signal obtained by mixing the second oscillation signal with the reference tone signal, and a receiver configured to generate a first reference IQ signal from the first loopback signal, generate a second reference IQ signal from the second loopback signal, and compare an actual phase difference between the first reference IQ signal and the second reference IQ signal with the defined phase difference.
-
14.发明公开公开(公告)号：US20230163790A1
公开(公告)日：2023-05-25
申请号：US18151711
申请日：2023-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngsea CHO , Jiseon Paek , Wan Kim , Daechul Jeong
CPC classification number: H04B1/0017 , H04B1/1676 , H04B1/62
Abstract: A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.
-
15.发明授权公开(公告)号：US11552655B2
公开(公告)日：2023-01-10
申请号：US17196463
申请日：2021-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngsea Cho , Jiseon Paek , Wan Kim , Daechul Jeong
Abstract: A digital radio frequency (RF) transmitter including processing circuitry configured to generate first through third pattern signals based on a pattern of an inphase (I)-quadrature (Q) binary data pair and a pattern of an inverted I-Q binary data pair, the first through third pattern signals having a same pattern and different phases, and a switched-capacitor digital-to-analog converter (SC-DAC) configured to remove an n-th harmonic component of an RF analog signal by amplifying the first through third pattern signals to have a certain magnitude ratio and synthesizing the amplified first through third pattern signals into the RF analog signal, where “n” is an integer of at least 3, may be provided.
-
公开(公告)号：US11509298B2
公开(公告)日：2022-11-22
申请号：US17514552
申请日：2021-10-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehoon Lee , Yong Lim , Wan Kim , Barosaim Sung , Seunghyun Oh
Abstract: A comparator configured to calibrate an offset according to a control signal, including an input circuit configured to receive a first input signal and a second input signal, and to generate a first internal signal corresponding to the first input signal and a second internal signal corresponding to the second input signal; a differential amplification circuit configured to consume a supply current flowing from a positive voltage node having a positive supply voltage to a negative voltage node having a negative supply voltage, and to generate an output signal by amplifying a difference between the first internal signal and the second internal signal; and a current valve configured to adjust at least a portion of the supply current based on the control signal.
-
-
-
-
-
Search Results
16
records
(took 0.021 seconds)
