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公开(公告)号:US20230009575A1
公开(公告)日:2023-01-12
申请号:US17690371
申请日:2022-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minhee CHO , Mintae RYU , Sungwon YOO , Wonsok LEE , Hyunmog PARK , Kiseok LEE
IPC: H01L29/786
Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.
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公开(公告)号:US20220302198A1
公开(公告)日:2022-09-22
申请号:US17528237
申请日:2021-11-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeongsoon KANG , Mintae RYU , Minsu LEE , Wonsok LEE
IPC: H01L27/146 , H01L27/148
Abstract: An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.
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公开(公告)号:US20220149092A1
公开(公告)日:2022-05-12
申请号:US17376333
申请日:2021-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jeongsoon KANG , Buil JUNG , Hyunmog PARK , Wonsok LEE
IPC: H01L27/146
Abstract: An image sensor includes a substrate having a pixel area in which a plurality of active areas is defined. A first transistor includes a first gate electrode including a buried gate portion. The buried gate portion is buried in the substrate in a first active area selected from the plurality of active areas. A second transistor includes a second gate electrode overlapping the buried gate portion on the first active area in a vertical direction.
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