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    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220367721A1

    公开(公告)日：2022-11-17

    申请号：US17694903

    申请日：2022-03-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae Kyeong JEONG ,  Min Tae RYU ,  Hyeon Joo SEUL ,  Sungwon YOO ,  Wonsok LEE ,  Min Hee CHO ,  Jae Seok HUR

    IPC: H01L29/786

    Abstract: Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

    SEMICONDUCTOR DEVICE
    4.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240170578A1

    公开(公告)日：2024-05-23

    申请号：US18378170

    申请日：2023-10-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungbeck LEE ,  Mintae RYU ,  Minjin KWON ,  Hyeonjeong SUN ,  Wonsok LEE ,  Minhee CHO

    IPC: H01L29/786 ,  H01L27/06 ,  H01L29/66

    CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696

    Abstract: A semiconductor device includes: a first insulation layer disposed on a substrate; a lower gate pattern disposed on the first insulation layer; a second insulation layer covering at least a portion of the lower gate pattern; a first lower gate insulation layer disposed on the lower gate pattern and the second insulation layer; a source pattern and a drain pattern disposed on the first lower gate insulation layer, wherein the source pattern and the drain pattern are spaced apart from each other to include a trench facing the lower gate pattern; an oxide semiconductor layer formed along surfaces of the source and drain patterns and a bottom surface of the trench; an upper gate insulation layer disposed on the oxide semiconductor layer; and an upper gate pattern disposed on the upper gate insulation layer and filling the trench.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230055499A1

    公开(公告)日：2023-02-23

    申请号：US17805706

    申请日：2022-06-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

    Abstract: A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    6.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240282833A1

    公开(公告)日：2024-08-22

    申请号：US18364612

    申请日：2023-08-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sanghoon UHM ,  Min Hee CHO ,  Wonsok LEE ,  Wooje JUNG

    IPC: H01L29/423 ,  H01L29/51 ,  H10B12/00

    CPC classification number: H01L29/42364 ,  H01L29/518 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

    Abstract: A semiconductor device may include a bit line on the substrate, a channel pattern on the bit line and extending in a direction perpendicular to the bit line, a word line intersecting the bit line and spaced apart from the channel pattern, a gate insulating pattern between the channel pattern and the word line, an insulating pattern on the word line, and a landing pad connected to the channel pattern. The gate insulating pattern may include a first gate insulating pattern and a second gate insulating pattern having a first dielectric constant and a second dielectric constant, respectively. The second gate insulating pattern may be between the first gate insulating pattern and the word line. The first and second dielectric constants may be different. A first width of the first gate insulating pattern may be different from a second width of the second gate insulating pattern.

    SEMICONDUCTOR MEMORY DEVICE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240422964A1

    公开(公告)日：2024-12-19

    申请号：US18421187

    申请日：2024-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyunghwan LEE ,  Wonsok LEE ,  Juho LEE ,  Daewon HA

    IPC: H10B12/00 ,  H01L29/10

    Abstract: A semiconductor memory device includes a memory cell array having a three-dimensional structure, the memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells includes two transistors including at a least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit line extending along the second lateral direction, and each of the plurality of memory cells does not include a capacitor.

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230055147A1

    公开(公告)日：2023-02-23

    申请号：US17741701

    申请日：2022-05-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

    IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

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