公开(公告)号：US20230009575A1

公开(公告)日：2023-01-12

申请号：US17690371

申请日：2022-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee CHO ,  Mintae RYU ,  Sungwon YOO ,  Wonsok LEE ,  Hyunmog PARK ,  Kiseok LEE

IPC: H01L29/786

Abstract: A semiconductor device including a conductive line on a substrate, a first gate electrode on the conductive line, a second gate electrode separated by a gate isolation insulating layer on the first gate electrode, a first channel layer on a side surface of the first gate electrode, with a first gate insulating layer therebetween, a first source/drain region on another side surface of the first gate electrode, a second channel layer on another side surface of the second gate electrode on a side that is opposite to the first channel layer, with a second gate insulating layer therebetween, a second source/drain region on the second channel layer, and a third source/drain region on the first channel layer and on a side surface of the second gate electrode on a same side as the first channel layer may be provided.

公开(公告)号：US20220302198A1

公开(公告)日：2022-09-22

申请号：US17528237

申请日：2021-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongsoon KANG ,  Mintae RYU ,  Minsu LEE ,  Wonsok LEE

IPC: H01L27/146 ,  H01L27/148

Abstract: An image sensor includes a first substrate. A photoelectric conversion region is in the first substrate. A first interlayer insulating layer is on the first substrate. A transistor includes a bonding insulating layer on the first interlayer insulating layer, a semiconductor layer on the bonding insulating layer, and a first gate on the semiconductor layer. A bias pad is spaced apart from the semiconductor layer by the bonding insulating layer. The bias pad overlaps the first gate in a planar view. A second interlayer insulating layer covers the transistor.

公开(公告)号：US20240170578A1

公开(公告)日：2024-05-23

申请号：US18378170

申请日：2023-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungbeck LEE ,  Mintae RYU ,  Minjin KWON ,  Hyeonjeong SUN ,  Wonsok LEE ,  Minhee CHO

IPC: H01L29/786 ,  H01L27/06 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/0688 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device includes: a first insulation layer disposed on a substrate; a lower gate pattern disposed on the first insulation layer; a second insulation layer covering at least a portion of the lower gate pattern; a first lower gate insulation layer disposed on the lower gate pattern and the second insulation layer; a source pattern and a drain pattern disposed on the first lower gate insulation layer, wherein the source pattern and the drain pattern are spaced apart from each other to include a trench facing the lower gate pattern; an oxide semiconductor layer formed along surfaces of the source and drain patterns and a bottom surface of the trench; an upper gate insulation layer disposed on the oxide semiconductor layer; and an upper gate pattern disposed on the upper gate insulation layer and filling the trench.

公开(公告)号：US20230328950A1

公开(公告)日：2023-10-12

申请号：US18175445

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Mintae RYU ,  Yongjin LEE

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor memory device includes a plurality of memory cells arranged on a substrate. Each of the plurality of memory cells may include a first transistor on the substrate and a second transistor on the first transistor. The first transistor may include a first channel region between a first source region and a first drain region, a first gate electrode, and a first gate insulating layer. The second transistor may include a pillar structure having a second drain region, a second channel region and a second source region sequentially stacked on the first gate electrode, a second gate electrode on one side of the second channel region, and a second gate insulating layer between the second channel region and the second gate electrode. The second drain region and the second source region may have a first conductivity type impurity region and a second conductivity type impurity region, respectively.