公开(公告)号：US20180375523A1

公开(公告)日：2018-12-27

申请号：US15861962

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsik Yu ,  Wooseok Kim ,  Jihyun Kim ,  Taeik Kim ,  Kangyeop Choo

IPC: H03L7/095 ,  H03K5/135 ,  H03L7/18

Abstract: A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.

公开(公告)号：US20250036022A1

公开(公告)日：2025-01-30

申请号：US18632558

申请日：2024-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghwa Woo ,  Wooseok Kim ,  Bongkeun Kim ,  Sanghwa Lee

IPC: G03F1/36

Abstract: Provided is an optical proximity correction (OPC) method including receiving a design layout for a target pattern to be formed on a substrate, obtaining a first OPC pattern by performing a baseline OPC on the design layout, and obtaining a second OPC pattern by curving the first OPC pattern.

公开(公告)号：US12192315B2

公开(公告)日：2025-01-07

申请号：US17943932

申请日：2022-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dokyung Lim ,  Sounghun Shin ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

IPC: H03D3/24 ,  H04L7/033 ,  H04L43/087

Abstract: A monitoring circuit for a high frequency signal includes: a phase locked loop configured to generate a divided output signal with respect to an input signal based on a plurality of dividers; a plurality of dividing monitoring circuits configured to receive dividing input signals and dividing output signals respectively corresponding to the plurality of dividers, and output dividing error signals; and a jitter monitoring circuit configured to output a jitter error signal.

公开(公告)号：US11736112B2

公开(公告)日：2023-08-22

申请号：US17675351

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyeop Choo ,  Wooseok Kim ,  Wonsik Yu ,  Chanyoung Jeong

IPC: H03L7/099 ,  H03B5/04 ,  H03L7/093

CPC classification number: H03L7/0992 ,  H03B5/04 ,  H03L7/093

Abstract: A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

公开(公告)号：US10158367B1

公开(公告)日：2018-12-18

申请号：US15861962

申请日：2018-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsik Yu ,  Wooseok Kim ,  Jihyun Kim ,  Taeik Kim ,  Kangyeop Choo

IPC: H03L7/18 ,  H03L7/23 ,  H03L7/095 ,  H03K5/135

CPC classification number: H03L7/235 ,  H03K5/135 ,  H03L7/095 ,  H03L7/18 ,  H03L2207/08

Abstract: A digital phase locked loop includes a digital phase detector, a digital loop filter, a digital controlled oscillator, a first divider that divides the second frequency of the oscillation signal depending on a first division value and outputs the division result as a division signal having a third frequency, a second divider that divides the second frequency of the oscillation signal depending on a second division value and outputs the division result as an output signal having a final frequency, a dithering block that receives the division signal and performs dithering on the first division value based on a preset pattern as cycles of the division signal pass, and a digital phase domain filter that performs second low pass filtering on the division signal in a phase domain and outputs the result of the second low pass filtering as the feedback signal.