公开(公告)号：US20230088032A1

公开(公告)日：2023-03-23

申请号：US18059747

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20230065076A1

公开(公告)日：2023-03-02

申请号：US18054295

申请日：2022-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Seunghun Shin ,  Junyeong Heo

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

公开(公告)号：US20220399311A1

公开(公告)日：2022-12-15

申请号：US17667989

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyeong HEO ,  Yeongkwon KO ,  Unbyoung KANG ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/78

Abstract: A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and an insulating adhesive layer between the first semiconductor chip, and each of the plurality of second semiconductor chips, each of the plurality second conductor chips, and the insulating adhesive layer including an adhesive fillet protruding from between at least the first semiconductor chip and each of the plurality of second semiconductor chips, wherein a grooving recess is defined by the first semiconductor chip, the plurality of second semiconductor chips, and the insulating adhesive layer, the grooving recess including a first recess and a second recess adjacent to the first recess, an uppermost surface of the adhesive fillet and the first semiconductor chip defines the first recess, and an uppermost surface of the first semiconductor chip to a surface inside the first semiconductor chip defines the second recess.

公开(公告)号：US20220020701A1

公开(公告)日：2022-01-20

申请号：US17203007

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20210366876A1

公开(公告)日：2021-11-25

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.