公开(公告)号：US20240162194A1

公开(公告)日：2024-05-16

申请号：US18421198

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20220013474A1

公开(公告)日：2022-01-13

申请号：US17083932

申请日：2020-10-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Yeongkwon KO ,  Jayeon LEE ,  Jaeeun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package comprises a substrate; an interposer on the substrate; a first underfill between the substrate and the interposer; at least one logic chip and at least one memory stack on the interposer; and a molding material on the interposer while surrounding a side surface of the at least one logic chip and a side surface of the at least one memory stack. The molding material includes areas having different heights. The first underfill covers a portion of the molding material.

公开(公告)号：US20250062248A1

公开(公告)日：2025-02-20

申请号：US18934816

申请日：2024-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20230146621A1

公开(公告)日：2023-05-11

申请号：US18049901

申请日：2022-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyung YOO ,  Jinwoo PARK ,  Jayeon LEE ,  Jaeeun LEE

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L23/48

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L23/293 ,  H01L23/481 ,  H01L2224/32225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/2929 ,  H01L24/29 ,  H01L2224/29386

Abstract: A semiconductor device includes a plurality of semiconductor chips sequentially stacked on a substrate, an underfill layer between the plurality of semiconductor chips and between the substrate and a lowermost one of the plurality of semiconductor chips, and a molding resin extending around the plurality of semiconductor chips. The molding resin extends to a space between an uppermost one of the plurality of semiconductor chips and a semiconductor chip sequentially beneath the uppermost one of the plurality of semiconductor chips.

公开(公告)号：US20240079299A1

公开(公告)日：2024-03-07

申请号：US18125917

申请日：2023-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaekyung YOO ,  Woohyeong KIM ,  Jinwoo PARK ,  Juhyeon OH ,  Jayeon LEE

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227 ,  H10B80/00

Abstract: A semiconductor package includes a first redistribution wiring layer having a first surface and a second surface opposite to the first surface, the first redistribution wiring layer having protrusions protruding from the first surface and a plurality of first bonding pads provided on the protrusions, a first semiconductor device mounted on the first redistribution wiring layer via conductive bumps, a plurality of conductive structures respectively extending from the first bonding pads around the first semiconductor device, and a second redistribution wiring layer disposed on the conductive structures and electrically connected to the first redistribution wiring layer.

公开(公告)号：US20230178499A1

公开(公告)日：2023-06-08

申请号：US18162878

申请日：2023-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/13

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0652 ,  H01L23/13 ,  H01L2924/3512 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20230088032A1

公开(公告)日：2023-03-23

申请号：US18059747

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US20220020701A1

公开(公告)日：2022-01-20

申请号：US17203007

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongkwon KO ,  Un-Byoung KANG ,  Jaekyung YOO ,  Teak Hoon LEE

IPC: H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.

公开(公告)号：US20210366876A1

公开(公告)日：2021-11-25

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung YOO ,  Jayeon LEE ,  Jae-eun LEE ,  Yeongkwon KO ,  Jin-woo PARK ,  Teak Hoon LEE

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.