公开(公告)号：US11380700B2

公开(公告)日：2022-07-05

申请号：US16842907

申请日：2020-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Youngbum Woo

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/07

Abstract: A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.

公开(公告)号：US20210287986A1

公开(公告)日：2021-09-16

申请号：US17060851

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US20210202458A1

公开(公告)日：2021-07-01

申请号：US17030887

申请日：2020-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uidam Jung ,  Youngbum Woo ,  Byungkyu Kim ,  Eunji Kim ,  Seungwoo Paek

IPC: H01L25/18 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/00

Abstract: A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.