公开(公告)号：US09972638B2

公开(公告)日：2018-05-15

申请号：US14621568

申请日：2015-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghae Lee ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC: H01L21/8238 ,  H01L27/11582 ,  H01L29/78 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

公开(公告)号：US11469172B2

公开(公告)日：2022-10-11

申请号：US17060851

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/10

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US10256250B2

公开(公告)日：2019-04-09

申请号：US15708266

申请日：2017-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihyun Kim ,  Chadong Yeo

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11578

Abstract: A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.

公开(公告)号：US20180240808A1

公开(公告)日：2018-08-23

申请号：US15714254

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyeong SONG ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  G11C16/12

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

公开(公告)号：US20230040582A1

公开(公告)日：2023-02-09

申请号：US17963062

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/10

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US20210287986A1

公开(公告)日：2021-09-16

申请号：US17060851

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US10396093B2

公开(公告)日：2019-08-27

申请号：US15714254

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minyeong Song ,  Chadong Yeo ,  Jaeduk Lee ,  Jaehoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  G11C16/12 ,  H01L27/1157 ,  G11C16/04 ,  G11C16/10

Abstract: A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

公开(公告)号：US11862556B2

公开(公告)日：2024-01-02

申请号：US17963062

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/10

CPC classification number: H01L23/5226 ,  H01L23/53209 ,  H01L23/53295 ,  H01L29/1033

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US10998330B2

公开(公告)日：2021-05-04

申请号：US15476044

申请日：2017-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunmog Park ,  Daewoong Kang ,  Chadong Yeo ,  Jaehoon Jang ,  Joongshik Shin

IPC: H01L29/04 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/16 ,  H01L29/49 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157

Abstract: A {111} plane of a substrate having a silicon crystal structure meets a top surface of the substrate to form an interconnection line on the top surface. A first stacked structure and a second stacked structure is formed on the substrate. Each of the first and the second stacked structures includes gate electrodes stacked on the substrate. A transistor is disposed on the substrate and positioned between the first stacked structure and the second stacked structure. The transistor includes a gate electrode extending in a first direction, a source region and a drain region. The source and the drain regions are disposed at both sides of the gate electrode in a second direction crossing the first direction. The interconnection line is extended at an angle with respect to the second direction.

公开(公告)号：US20190221579A1

公开(公告)日：2019-07-18

申请号：US16362932

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihyun KIM ,  Chadong Yeo

IPC: H01L27/11582 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578

Abstract: A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.