-
公开(公告)号：US11862556B2
公开(公告)日：2024-01-02
申请号：US17963062
申请日：2022-10-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taemok Gwon , Junhyoung Kim , Chadong Yeo , Youngbum Woo
IPC: H01L23/522 , H01L23/532 , H01L29/10
CPC classification number: H01L23/5226 , H01L23/53209 , H01L23/53295 , H01L29/1033
Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.
-
公开(公告)号：US20240389365A1
公开(公告)日：2024-11-21
申请号：US18786162
申请日：2024-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungmin Lee , Junhyoung Kim , Youngbum Woo , Joonsung Lim
Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, and first metal bonding layers disposed on the circuit devices, and a second semiconductor structure including gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to upper surfaces of the first metal bonding layers, channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer, second metal bonding layers disposed below the channel structures and the gate electrodes and connected to the first metal bonding layers, bit lines disposed below the channel structures, extending in a second direction, perpendicular to the first direction, and spaced apart from each other, and source lines disposed on the channel structures, extending in a third direction, perpendicular to the second direction, and spaced apart from each other. The channel structures are respectively disposed in intersection regions in which the bit lines and the source lines intersect each other.
-
公开(公告)号：US11469172B2
公开(公告)日：2022-10-11
申请号：US17060851
申请日：2020-10-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taemok Gwon , Junhyoung Kim , Chadong Yeo , Youngbum Woo
IPC: H01L23/48 , H01L23/522 , H01L23/532 , H01L29/10
Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.
-
公开(公告)号：US20240379647A1
公开(公告)日：2024-11-14
申请号：US18780646
申请日：2024-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Uidam Jung , Youngbum Woo , Byungkyu Kim , Eunji Kim , Seungwoo Paek
Abstract: A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.
-
公开(公告)号：US11527524B2
公开(公告)日：2022-12-13
申请号：US17030887
申请日：2020-09-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Uidam Jung , Youngbum Woo , Byungkyu Kim , Eunji Kim , Seungwoo Paek
IPC: H01L25/18 , H01L27/11565 , H01L27/11582 , H01L23/00
Abstract: A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.
-
Patent Agency Ranking
公开(公告)号：US12133381B2
公开(公告)日：2024-10-29
申请号：US17497200
申请日：2021-10-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Moorym Choi , Taemok Gwon , Junhyoung Kim , Hyunjae Kim , Youngbum Woo , Jongin Yun
IPC: H10B41/27 , G11C5/06 , H01L23/538 , H01L29/06 , H10B43/27
CPC classification number: H10B41/27 , G11C5/06 , H01L23/5384 , H01L23/5386 , H01L29/0649 , H10B43/27
Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.
-
公开(公告)号：US20210036001A1
公开(公告)日：2021-02-04
申请号：US16842907
申请日：2020-04-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhyoung Kim , Taemok Gwon , Youngbum Woo
IPC: H01L27/11556 , H01L27/11582 , H01L27/07 , H01L23/522
Abstract: A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.
-
公开(公告)号：US12080699B2
公开(公告)日：2024-09-03
申请号：US18054172
申请日：2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Uidam Jung , Youngbum Woo , Byungkyu Kim , Eunji Kim , Seungwoo Paek
IPC: H01L25/18 , H01L23/00 , H01L27/11582 , H10B43/10 , H10B43/27
CPC classification number: H01L25/18 , H01L24/05 , H01L24/08 , H01L24/29 , H01L24/32 , H10B43/10 , H10B43/27 , H01L2224/0557 , H01L2224/08145 , H01L2224/29186 , H01L2224/32145 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.
-
公开(公告)号：US20230067443A1
公开(公告)日：2023-03-02
申请号：US18054172
申请日：2022-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Uidam Jung , Youngbum Woo , Byungkyu Kim , Eunji Kim , Seungwoo Paek
IPC: H01L25/18 , H01L27/11582 , H01L27/11565 , H01L23/00
Abstract: A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.
-
公开(公告)号：US20230040582A1
公开(公告)日：2023-02-09
申请号：US17963062
申请日：2022-10-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Taemok Gwon , Junhyoung Kim , Chadong Yeo , Youngbum Woo
IPC: H01L23/522 , H01L23/532 , H01L29/10
Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.014 seconds)
