公开(公告)号：US11469172B2

公开(公告)日：2022-10-11

申请号：US17060851

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L29/10

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US11862556B2

公开(公告)日：2024-01-02

申请号：US17963062

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/10

CPC classification number: H01L23/5226 ,  H01L23/53209 ,  H01L23/53295 ,  H01L29/1033

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US20230040582A1

公开(公告)日：2023-02-09

申请号：US17963062

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L23/532 ,  H01L29/10

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US11380700B2

公开(公告)日：2022-07-05

申请号：US16842907

申请日：2020-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Youngbum Woo

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L27/07

Abstract: A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.

公开(公告)号：US20210287986A1

公开(公告)日：2021-09-16

申请号：US17060851

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemok Gwon ,  Junhyoung Kim ,  Chadong Yeo ,  Youngbum Woo

IPC: H01L23/522 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

公开(公告)号：US12133381B2

公开(公告)日：2024-10-29

申请号：US17497200

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym Choi ,  Taemok Gwon ,  Junhyoung Kim ,  Hyunjae Kim ,  Youngbum Woo ,  Jongin Yun

IPC: H10B41/27 ,  G11C5/06 ,  H01L23/538 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/06 ,  H01L23/5384 ,  H01L23/5386 ,  H01L29/0649 ,  H10B43/27

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

公开(公告)号：US20240312938A1

公开(公告)日：2024-09-19

申请号：US18674610

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Seungmin Lee

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  H01L23/5226 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes first gate electrodes, a first channel structure penetrating the first gate electrodes and including a first channel layer and a first channel filling insulating layer, second gate electrodes above the first gate electrodes, a second channel structure penetrating the second gate electrodes and including a second channel layer and a second channel filling insulating layer, and a central wiring layer between the first gate electrodes and the second gate electrodes and connected to the first channel layer and the second channel layer, wherein the first channel layer and the second channel layer are connected to each other in a region surrounded by the central wiring layer, and the first channel filling insulating layer and the second channel filling insulating layer are connected to each other in a region surrounded by the central wiring layer.

公开(公告)号：US20210036001A1

公开(公告)日：2021-02-04

申请号：US16842907

申请日：2020-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Taemok Gwon ,  Youngbum Woo

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/07 ,  H01L23/522

Abstract: A vertical memory device includes lower circuit patterns, a second substrate, a capacitor, gate electrodes, and a channel. The lower circuit patterns are formed on a first substrate including first, second and third regions. Contact plugs are formed in the second region. Through vias are formed in the third region. The second substrate is formed on the lower circuit patterns. The capacitor is formed on the lower circuit patterns, and includes a first conductor, a dielectric layer structure, and a second conductor. The first conductor is spaced apart from the second substrate at the same height as the second substrate. The dielectric layer structure is formed on the first conductor. The second conductor is formed on the dielectric layer structure. The gate electrodes are spaced apart from each other on the second substrate in a vertical direction. The channel extends through the gate electrodes in the vertical direction.