公开(公告)号：US20220059144A1

公开(公告)日：2022-02-24

申请号：US17229055

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunyoon CHO ,  Sukhee CHO ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C7/10 ,  G11C7/14

Abstract: A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.

公开(公告)号：US20250103091A1

公开(公告)日：2025-03-27

申请号：US18756305

申请日：2024-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tongsung KIM ,  Woojung KIM ,  Yoonji PARK ,  Younghoon SON ,  Seonkyoo LEE ,  Ilyoung JIN

IPC: G06F1/08 ,  G06F1/10

Abstract: Provided are an apparatus and a method for adjusting a skew between data and a clock. The apparatus driven by a supply voltage includes a clock circuit that adjusts a skew between data and a clock. The clock circuit performs a first loop operation through a first loop and a second loop operation through a second loop, based on a phase difference between data and a clock. The first loop operation is performed until there is no phase difference between the data and the clock, and the second loop operation is performed until a first slope representing a change in delay of the data with respect to the levels of the power voltage and a second slope representing a change in delay of the clock become identical to each other.

公开(公告)号：US20230395133A1

公开(公告)日：2023-12-07

申请号：US18449066

申请日：2023-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung PARK ,  Younghoon SON ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C11/4093 ,  G06F13/16 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G06F13/1668 ,  G11C11/4076

Abstract: In a method of generating a multi-level signal having one of three or more voltage levels that are different from one another, input data including two or more bits is received. A drive strength of at least one of two or more driving paths is changed based on the two or more bits such that a first transition time, during which an output data signal is transitioned from a first voltage level to a second voltage level, is changed. The output data signal that is the multi-level signal is generated such that the first transition time of the output data signal is changed and a second transition time, during which the output data signal is transitioned from the first voltage level to a third voltage level different from the second voltage level, is maintained.

公开(公告)号：US20220414032A1

公开(公告)日：2022-12-29

申请号：US17903240

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G06F13/16 ,  H04L25/49

Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

公开(公告)号：US20220059139A1

公开(公告)日：2022-02-24

申请号：US17323009

申请日：2021-05-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyoung PARK ,  Jaewoo PARK ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

IPC: G11C5/14 ,  H04L25/49 ,  H04L25/02 ,  G11C11/56 ,  G11C7/10

Abstract: A method of generating a multi-level signal having one of three or more voltage levels that are different from each other, the method including: performing a first voltage setting operation in which first and second voltage intervals are adjusted to be different from each other, wherein the first voltage interval represents a difference between a first pair of adjacent voltage levels and the second voltage interval represents a difference between a second pair of adjacent voltage levels; performing a second voltage setting operation in which a voltage swing width is adjusted, the voltage swing width representing a difference between a lowest and a highest voltage level among the three or more voltage levels; and generating an output data signal that is the multi-level signal based on input data including two or more bits, a result of the first voltage setting operation and a result of the second voltage setting operation.