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    ELECTRONIC DEVICE FOR OPTIMIZING SEMICONDUCTOR CHARACTERISTICS BASED ON PLACKETT-BURMAN DESIGN AND GENETIC ALGORITHM, AND OPERATING METHOD THEREOF
    3.
    发明申请
    ELECTRONIC DEVICE FOR OPTIMIZING SEMICONDUCTOR CHARACTERISTICS BASED ON PLACKETT-BURMAN DESIGN AND GENETIC ALGORITHM, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20250165685A1

    公开(公告)日：2025-05-22

    申请号：US18952627

    申请日：2024-11-19

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Byeongnoh KIM ,  Suhyun CHAE ,  Dohan KIM ,  Younghoon SON ,  Jeeyong LEE ,  Insu CHOI

    IPC: G06F30/32 ,  G06N3/12

    Abstract: An electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device. The GA execution circuit is configured to convert a previous generation DOE set to a next generation DOE set. The control circuit is configured to transmit the initial DOE set to the external device, receive, from the external device, an initial characteristic evaluation, generate a starting DOE set based on the initial characteristic evaluation, and control a genetic algorithm to be performed with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.

    MEMORY PACKAGE AND STORAGE DEVICE INCLUDING THE SAME
    4.
    发明申请
    MEMORY PACKAGE AND STORAGE DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20220157353A1

    公开(公告)日：2022-05-19

    申请号：US17361780

    申请日：2021-06-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joohwan KIM ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G11C7/10 ,  G06F3/06 ,  G11C7/22

    Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.

    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM
    5.
    发明申请
    MEMORY DEVICE, OPERATING METHOD OF THE SAME, AND MEMORY SYSTEM 有权

    公开(公告)号：US20220068331A1

    公开(公告)日：2022-03-03

    申请号：US17230403

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mingyu LEE ,  Jaewoo PARK ,  Younghoon SON ,  Youngdon CHOI ,  Hyungmin JIN ,  Junghwan CHOI

    IPC: G11C7/22 ,  G11C7/06 ,  G06F13/16

    Abstract: A method of operating a memory device including receiving a multilevel signal having M levels transmitted by an external controller through a clock receiving pin, where M is a natural number greater than 2, and decoding the multilevel signal to restore at least one of Data Bus Inversion (DBI) data, Data Mask (DM) data, Cyclic Redundancy Check (CRC) data, or Error Correction Code (ECC) data may be provided. The multilevel signal is a clock signal transmitted by the external controller, and is a signal swinging based on an intermediate reference signal that is an intermediate value between a minimum level and a maximum level among the M levels.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    6.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20240370386A1

    公开(公告)日：2024-11-07

    申请号：US18772354

    申请日：2024-07-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE
    10.
    发明申请
    MEMORY DEVICE SUPPORTING A HIGH-EFFICIENT INPUT/OUTPUT INTERFACE AND A MEMORY SYSTEM INCLUDING THE MEMORY DEVICE 有权

    公开(公告)号：US20220121582A1

    公开(公告)日：2022-04-21

    申请号：US17326513

    申请日：2021-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungmin JIN ,  Jindo BYUN ,  Younghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G06F13/16 ,  H04L25/49

    Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.

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