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    TRANSMITTER, MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE TRANSMITTER
    1.
    发明公开
    TRANSMITTER, MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE TRANSMITTER 审中-公开

    公开(公告)号：US20240203466A1

    公开(公告)日：2024-06-20

    申请号：US18230776

    申请日：2023-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung PARK ,  Garam KIM ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Junghwan CHOI

    IPC: G11C7/10 ,  H03K19/017

    CPC classification number: G11C7/1066 ,  G11C7/1063 ,  H03K19/01742

    Abstract: A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

    TRANSMITTER CIRCUIT INCLUDING SELECTION CIRCUIT, AND METHOD OF OPERATING THE SELECTION CIRCUIT
    5.
    发明申请
    TRANSMITTER CIRCUIT INCLUDING SELECTION CIRCUIT, AND METHOD OF OPERATING THE SELECTION CIRCUIT 有权

    公开(公告)号：US20220385287A1

    公开(公告)日：2022-12-01

    申请号：US17751148

    申请日：2022-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung PARK ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K17/693 ,  H03K19/20

    Abstract: A transmitter circuit includes a clock generator configured to generate a plurality of clock signals having different phases, and a plurality of selection circuits configured to receive a plurality of parallel data signals and output a serial data signal on an output node based on the plurality of clock signals and the received plurality of parallel data signals. Each of the plurality of selection circuits includes a data multiplexer configured to generate a plurality of data selection signals based on the received one of the plurality of parallel data signals and the plurality of clock signals; a control signal generator configured to generate first and second control signals based on the plurality of data selection signals; and an output driver connected to the output node, and configured to precharge the output node based on the first control signal or discharge the output node based on the second control signal.

    RECEIVER WITH PIPELINE STRUCTURE FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME
    6.
    发明申请
    RECEIVER WITH PIPELINE STRUCTURE FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230116188A1

    公开(公告)日：2023-04-13

    申请号：US17943448

    申请日：2022-09-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsub RIE ,  Eunseok SHIN ,  Youngdon CHOI ,  Changsoo YOON ,  Hyunyoon CHO ,  Junghwan CHOI

    IPC: G11C11/4096 ,  H03M1/12

    Abstract: A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

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