MEMORY DEVICE, MEMORY DEVICE TEST METHOD, AND TEST SYSTEM

    公开(公告)号:US20240220117A1

    公开(公告)日:2024-07-04

    申请号:US18467959

    申请日:2023-09-15

    CPC classification number: G06F3/0611 G06F3/0655 G06F3/0679

    Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, configured to sample the input data based on the first clock signal, and configured to generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array, where i is a natural number greater than or equal to 2.

    Refrigerator
    12.
    外观设计

    公开(公告)号:USD1033491S1

    公开(公告)日:2024-07-02

    申请号:US29873428

    申请日:2023-03-31

    Abstract: FIG. 1 is a front perspective view of a refrigerator, showing our new design;
    FIG. 2 is a front view thereof;
    FIG. 3 is a rear view thereof;
    FIG. 4 is a side view thereof;
    FIG. 5 is another side view thereof;
    FIG. 6 is a top view thereof;
    FIG. 7 is a bottom view thereof; and,
    FIG. 8 is another front perspective view thereof as shown in an alternate configuration.
    The broken lines depict portions of the refrigerator that form no part of the claimed design.

    Memory device, memory device test method, and test system

    公开(公告)号:US12300344B2

    公开(公告)日:2025-05-13

    申请号:US18467959

    申请日:2023-09-15

    Abstract: A memory device according to an embodiment includes a memory cell array; a timing circuit configured to generate a first clock signal and a second clock signal, the second clock signal having a frequency that is i-times the frequency of the first clock signal; a command decoder configured to receive On-The-Fly (OTF) data including a plurality of OTF bits; a receiver configured to receive input data, sample the input data based on the first clock signal, and generate a first signal based on the sampled input data; a deserializer configured to generate a first deserialized signal from the first signal based on the second clock signal; a data pattern generator configured to generate a pattern signal based on the first deserialized signal and the OTF data based on the second clock signal; and a decoder configured to transmit the pattern signal to the memory cell array.

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