公开(公告)号：US12125537B2

公开(公告)日：2024-10-22

申请号：US17502398

申请日：2021-10-15

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483

Abstract: The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.

公开(公告)号：US20240212768A1

公开(公告)日：2024-06-27

申请号：US18357412

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Deepanshu Dutta ,  Bo Lei

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/3404

Abstract: A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

公开(公告)号：US11626160B2

公开(公告)日：2023-04-11

申请号：US17166612

申请日：2021-02-03

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Bo Lei ,  Jun Wan

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

Abstract: Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.