公开(公告)号：US12046297B2

公开(公告)日：2024-07-23

申请号：US17824350

申请日：2022-05-25

Applicant: SanDisk Technologies LLC

Inventor： Peng Wang ,  Jia Li ,  Behrang Bagheri ,  Keyur Payak ,  Bo Lei ,  Long Pham ,  Jun Wan

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/32 ,  H10B41/27 ,  H10B43/27

Abstract: An apparatus that comprises a plurality of memory cells and a control circuit coupled to the plurality of memory cells is disclosed. The control circuit is configured to perform a read operation. The read operation includes determining a read condition of a memory cell, where the read condition is of a plurality of read conditions and determining a boost timing for the memory cell, where the boost timing corresponds to the read condition.

公开(公告)号：US20240242764A1

公开(公告)日：2024-07-18

申请号：US18222735

申请日：2023-07-17

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Deepanshu Dutta ,  Jia Li ,  Bo Lei ,  Ken Oowada

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08

Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

公开(公告)号：US20240127895A1

公开(公告)日：2024-04-18

申请号：US18351179

申请日：2023-07-12

Applicant: SanDisk Technologies LLC

Inventor： Peng Wang ,  Zhenni Wan ,  Jia Li ,  Yihang Liu ,  Bo Lei

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: During a read operation for memory cells connected a selected word line, a memory system adjusts the overdrive voltage applied to word lines adjacent the selected word line in order to compensate for margin degradation between the erased data state and the lowest programmed data state.

公开(公告)号：US20230377655A1

公开(公告)日：2023-11-23

申请号：US17747088

申请日：2022-05-18

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Nidhi Agrawal ,  Zhenni Wan ,  Bo Lei ,  Jun Wan

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11556

Abstract: The memory device that includes a memory block memory cells arranged in word lines. A controller is in electrical communication with the memory cells and is configured to program the memory cells to a first set of data states in a first programming pass and then to a greater second set of data states in a second programming pass. During programming of a first set of memory cells in at least one of the first and second programming passes, the controller is further configured to determine programming statuses of a second set of memory cells that is adjacent the first set of memory cells. The controller is further configured to read the first set of memory cells using a read voltage that is adjusted from a base read voltage based on the determined programming statuses of the second set of memory cells.

公开(公告)号：US20230124371A1

公开(公告)日：2023-04-20

申请号：US17502398

申请日：2021-10-15

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04

Abstract: The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.

公开(公告)号：US09810723B2

公开(公告)日：2017-11-07

申请号：US13628465

申请日：2012-09-27

Applicant: SanDisk Technologies LLC

Inventor： Feng Pan ,  Jun Wang ,  Shankar Guhados ,  Bo Lei

IPC: G05F1/10 ,  G05F3/02 ,  G01R19/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/50

CPC classification number: G01R19/0092 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

Abstract: Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory.

公开(公告)号：US12125537B2

公开(公告)日：2024-10-22

申请号：US17502398

申请日：2021-10-15

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Jun Wan ,  Bo Lei

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0483

Abstract: The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.

公开(公告)号：US20240212768A1

公开(公告)日：2024-06-27

申请号：US18357412

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Deepanshu Dutta ,  Bo Lei

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/3404

Abstract: A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

公开(公告)号：US11842775B2

公开(公告)日：2023-12-12

申请号：US17506960

申请日：2021-10-21

Applicant: SanDisk Technologies LLC

Inventor： Nidhi Agrawal ,  Bo Lei ,  Zhenni Wan

IPC: G11C7/00 ,  G11C16/32 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/32 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26

Abstract: A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.

公开(公告)号：US20230126422A1

公开(公告)日：2023-04-27

申请号：US17506960

申请日：2021-10-21

Applicant: SanDisk Technologies LLC

Inventor： Nidhi Agrawal ,  Bo Lei ,  Zhenni Wan

IPC: G11C16/32 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08

Abstract: A memory device that dynamically adjusts the sense time to read an open block of a memory block is disclosed. The adjusted sense time is based upon various considerations, including the sense time of the closed block equivalent and the openness of the open block. This allows the memory device to maintain a fixed Vt as well as reduce failed bit count, i.e., read errors due to an insufficient sense time. Also, the dynamic adjustment of sense time can optimize system performance and increase efficiency.