公开(公告)号：US10971240B1

公开(公告)日：2021-04-06

申请号：US16726387

申请日：2019-12-24

Applicant: SanDisk Technologies LLC

Inventor： Mohan Dunga ,  Pitamber Shukla

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/12

Abstract: The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.

公开(公告)号：US20190385680A1

公开(公告)日：2019-12-19

申请号：US16009892

申请日：2018-06-15

Applicant: SanDisk Technologies LLC

Inventor： Mohan Vamsi Dunga ,  Piyush Dak ,  Pitamber Shukla

IPC: G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/34

Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.

公开(公告)号：US10460816B2

公开(公告)日：2019-10-29

申请号：US15967572

申请日：2018-04-30

Applicant: SanDisk Technologies LLC

Inventor： Pitamber Shukla ,  Mohan Dunga ,  Anubhav Khandelwal

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G06F3/06 ,  G11C11/4074 ,  G11C29/52 ,  G11C16/04

Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.

公开(公告)号：US20180181462A1

公开(公告)日：2018-06-28

申请号：US15391455

申请日：2016-12-27

Applicant: SanDisk Technologies LLC

Inventor： Pitamber Shukla ,  Joanna Lai ,  Henry Chin ,  Deepak Raghu ,  Abhilash Kashyap

IPC: G06F11/10 ,  G11C29/52 ,  G11C16/34 ,  G11C16/28 ,  G11C16/10

CPC classification number: G06F11/1068 ,  G11C16/10 ,  G11C16/28 ,  G11C16/3459 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0407

Abstract: Technology is described herein for operating non-volatile storage. In one embodiment, the memory system tracks which adjustments to default values for hard bit read reference voltages are most frequently successful to decode data in non-volatile memory cells. In response to a process that uses only hard bits failing to successfully decode data in a group of the non-volatile memory cells, the memory system attempts to decode the data in the group of non-volatile memory cells using dynamic hard bit read reference voltages and dynamic soft bit read reference voltages that correspond to only a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages. By only using a subset of the most frequently successful adjustments to the default values for the hard bit read reference voltages time and power is saved.