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公开(公告)号：US12051467B2
公开(公告)日：2024-07-30
申请号：US16892753
申请日：2020-06-04
发明人： Huai-Yuan Tseng , Henry Chin , Deepanshu Dutta
IPC分类号： G11C16/10 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
摘要： A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.
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公开(公告)号：US20240221803A1
公开(公告)日：2024-07-04
申请号：US18360273
申请日：2023-07-27
发明人： Hua-Ling Cynthia Hsu , Victor Avila , Henry Chin
IPC分类号： G11C7/10
CPC分类号： G11C7/1096 , G11C7/106 , G11C7/1069
摘要： An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to receive a read command directed to at least one logical page of data during a program operation to store the at least one logical page of data in a plurality of non-volatile memory cells. The control circuits are further configured to stop the program operation at an intermediate stage of programming, read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page and obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.
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3.发明授权公开(公告)号：US11972804B2
公开(公告)日：2024-04-30
申请号：US17846452
申请日：2022-06-22
发明人： Xuan Tian , Henry Chin , Liang Li , Vincent Yin , Wei Zhao , Tony Zou
IPC分类号： G11C16/14 , G11C16/04 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/34 , G11C29/50 , H10B41/27 , H10B43/27
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/349 , G11C29/50004 , G11C2029/5004 , H10B41/27 , H10B43/27
摘要： The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.
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公开(公告)号：US20240079062A1
公开(公告)日：2024-03-07
申请号：US17903618
申请日：2022-09-06
发明人： Jiacen Guo , Han-Ping Chen , Henry Chin , Guirong Liang , Xiang Yang
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/3459
摘要： The memory device includes at least one memory block with source and drain sides and a plurality of memory cells arranged in a plurality of word lines. The word lines are arranged in a plurality of independently programmable and erasable sub-blocks. Control circuitry is configured to program the memory cells of a selected sub-block and determine a location of the within the at least one memory block and determine a programming condition of at least one unselected sub-block. The control circuitry is also configured to program at least one word line in the selected sub-block in a plurality of program loops that include pre-charging processes. The control circuitry pre-charges a plurality of channels from either the source or drain side based on at least one of the location of the selected sub-block within the memory block and the programming condition of the at least one unselected sub-block.
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公开(公告)号：US20230352108A1
公开(公告)日：2023-11-02
申请号：US17733042
申请日：2022-04-29
发明人： Erika Penzo , Henry Chin , Jie Liu , Dong-Il Moon
CPC分类号： G11C16/349 , G11C16/0483 , G11C16/24 , G11C16/26
摘要： An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
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公开(公告)号：US11087849B2
公开(公告)日：2021-08-10
申请号：US16021282
申请日：2018-06-28
发明人： Henry Chin , Zhenming Zhou
摘要： A non-volatile memory system includes a control circuit connected to non-volatile memory cells. The control circuit is configured to simultaneously program memory cells connected to different word lines that are in different sub-blocks of different blocks in different planes of a die.
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公开(公告)号：US20210202022A1
公开(公告)日：2021-07-01
申请号：US16728716
申请日：2019-12-27
发明人： Ashish Baraskar , Henry Chin , Ching-Huang Lu
摘要： A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.
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8.发明授权公开(公告)号：US10964402B1
公开(公告)日：2021-03-30
申请号：US16794614
申请日：2020-02-19
发明人： Han-Ping Chen , Henry Chin , Ashish Baraskar
摘要： Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.
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公开(公告)号：US10748622B2
公开(公告)日：2020-08-18
申请号：US16283464
申请日：2019-02-22
发明人： Lei Lin , Zhuojie Li , Tai-Yuan Tseng , Henry Chin , Gerrit Jan Hemink
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34 , G11C16/26 , G11C11/56 , H01L27/11565 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.
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10.发明授权公开(公告)号：US10566059B2
公开(公告)日：2020-02-18
申请号：US16014028
申请日：2018-06-21
发明人： Vinh Diep , Ching Huang Lu , Henry Chin , Changyuan Chen
IPC分类号： G11C11/34 , G11C16/04 , H01L27/1157 , H01L29/423 , H01L27/11573 , H01L29/792 , H01L27/11582
摘要： Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.
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