公开(公告)号：US20060136659A1

公开(公告)日：2006-06-22

申请号：US11018591

申请日：2004-12-21

申请人： Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

发明人： Sanjeev Jain ,  Gilbert Wolrich ,  Debra Bernstein

IPC分类号： G06F12/00

CPC分类号： G11C15/00

摘要： A content addressable memory (CAM) includes a linked list structure for a pending queue to order memory commands for maximizing memory channel bandwidth by minimizing read/write stalls due to read-modify-write commands.

摘要翻译： 内容可寻址存储器（CAM）包括用于等待队列的链接列表结构，以通过最小化由于读取 - 修改 - 写入命令引起的读取/写入停顿来排序存储器命令以最大化存储器通道带宽。

公开(公告)号：US20060126512A1

公开(公告)日：2006-06-15

申请号：US11009861

申请日：2004-12-10

申请人： Sanjeev Jain ,  Mark Rosenbluth ,  Gilbert Wolrich ,  Hugh Wilkinson

发明人： Sanjeev Jain ,  Mark Rosenbluth ,  Gilbert Wolrich ,  Hugh Wilkinson

IPC分类号： H04J3/14 ,  H04J1/16 ,  H04L1/00 ,  H04L12/26

CPC分类号： H04L47/10 ,  H04L49/15 ,  H04L49/254 ,  H04L49/30 ,  H04L2012/5678

摘要： Method and apparatus to manage flow control for a network device are described.

公开(公告)号：US20060067348A1

公开(公告)日：2006-03-30

申请号：US10955936

申请日：2004-09-30

申请人： Sanjeev Jain ,  Gilbert Wolrich ,  Mark Rosenbluth

发明人： Sanjeev Jain ,  Gilbert Wolrich ,  Mark Rosenbluth

IPC分类号： H04L12/28

CPC分类号： H04L47/50

摘要： A system that queues data packets includes efficient memory access of queue control data structures.

摘要翻译： 排队数据包的系统包括队列控制数据结构的高效存储器访问。

公开(公告)号：US20190237952A1

公开(公告)日：2019-08-01

申请号：US16167841

申请日：2018-10-23

申请人： Sanjeev Jain

发明人： Sanjeev Jain

IPC分类号： H02G3/12 ,  E04F19/02 ,  E04F19/04 ,  F24F13/02 ,  F24F13/06 ,  H02G3/10

摘要： A wall mounted rail system for providing additional air flow and electrical outlets to a room. The system includes a first rail removably securable to a second rail, wherein each rail includes a front surface and a rear surface. The rear surface can secure to a wall and a decorative molding, such as chair rail molding, is secured to the front surface. A plurality of ports are disposed on a bottom face of the front surface and can supply power to a device connected to each port. Further, each port is electrically connected to one another. Tubing extends through an interior volume of each rail and plurality of apertures are disposed on a top face of the front surface thereof. Each aperture is in fluid communication with the tubing to allow air to flow from the tubing, through the apertures, and into the room.

公开(公告)号：US20160182351A1

公开(公告)日：2016-06-23

申请号：US14580792

申请日：2014-12-23

申请人： Ren Wang ,  Sameh Gobriel ,  Christian Maciocco ,  Tsung-Yuan C. Tai ,  Ben-Zion Friedman ,  Hang T. Nguyen ,  Namakkal N. Venkatesan ,  Michael A. O'Hanlon ,  Shrikant M. Shah ,  Sanjeev Jain

发明人： Ren Wang ,  Sameh Gobriel ,  Christian Maciocco ,  Tsung-Yuan C. Tai ,  Ben-Zion Friedman ,  Hang T. Nguyen ,  Namakkal N. Venkatesan ,  Michael A. O'Hanlon ,  Shrikant M. Shah ,  Sanjeev Jain

IPC分类号： H04L12/757 ,  H04L12/721 ,  H04L12/727

CPC分类号： H04L67/2852 ,  H04L41/0893 ,  H04L45/38 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/00

摘要： Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.

摘要翻译： 用于识别网络分组的高速缓存行的技术，用于从通信地耦合到网络控制器的网络设备的处理器上的缓存驱逐。 网络设备被配置为基于在处理网络分组之后不需要网络分组的确定来确定与网络分组相对应的高速缓存行是否要从高速缓存中逐出，并提供指示 基于从网络控制器接收到的逐出策略，缓存行将从缓存中逐出。

公开(公告)号：US20100306263A1

公开(公告)日：2010-12-02

申请号：US12475357

申请日：2009-05-29

申请人： David K. Cassetti ,  Sanjeev Jain ,  Christopher F. Clark ,  Lokpraveen Bhupathy Mosur

发明人： David K. Cassetti ,  Sanjeev Jain ,  Christopher F. Clark ,  Lokpraveen Bhupathy Mosur

IPC分类号： G06F7/20 ,  G06F17/30 ,  G06F12/08

CPC分类号： G06F7/02 ,  G06F2207/025

摘要： Apparatuses and methods to perform pattern matching are presented. In one embodiment, an apparatus comprises a memory to store a first pattern table comprising information indicative of whether a byte of input data matches a pattern and whether to ignore other matches of the pattern occur in remaining bytes of the input data. The apparatus further comprises one-byte match logic coupled to the memory, to determine, based on the information in the first pattern table, a one-byte match event with respect to the input data. The apparatus further comprises a control unit to filter the other matches of the pattern based on the information of the first pattern table.

摘要翻译： 提出了执行模式匹配的设备和方法。 在一个实施例中，一种设备包括存储器，用于存储第一模式表，其包括指示输入数据的字节是否匹配模式的信息，以及是否忽略在输入数据的剩余字节中发生的模式的其他匹配。 该装置还包括耦合到存储器的一字节匹配逻辑，以便基于第一模式表中的信息来确定相对于输入数据的一个字节的匹配事件。 该装置还包括控制单元，用于基于第一模式表的信息来过滤模式的其他匹配。

公开(公告)号：US07426215B2

公开(公告)日：2008-09-16

申请号：US10819428

申请日：2004-04-06

申请人： David Romano ,  Sanjeev Jain ,  Gilbert Wolrich ,  John Wishneusky

发明人： David Romano ,  Sanjeev Jain ,  Gilbert Wolrich ,  John Wishneusky

IPC分类号： H04L12/28

CPC分类号： H04L47/568 ,  H04L47/50 ,  H04L47/527

摘要： A method and apparatus for scheduling packets using a pre-sort scheduling array having one or more smoothing registers. The scheduling array includes a number of round buffers, each round buffer having an associated smoothing register. To schedule a packet for transmission, the packet's transmission round and relative position within that round are determined, and an identifier for the packet is placed at the appropriate position within the scheduling array. A bit of the associated smoothing register is set, the set bit corresponding to the entry receiving the packet identifier. During transmission, the set bits of the smoothing register associated with a current round buffer are read to identify packets that are to be dequeued.

摘要翻译： 一种使用具有一个或多个平滑寄存器的预排序调度阵列来调度分组的方法和装置。 调度阵列包括多个循环缓冲器，每个循环缓冲器具有相关联的平滑寄存器。 为了调度分组进行传输，确定分组在该轮次内的传输轮和相对位置，并且将分组的标识符放置在调度阵列内的适当位置。 设置相关平滑寄存器的一位，该设置位对应于接收分组标识符的条目。 在传输期间，读取与当前循环缓冲器相关联的平滑寄存器的置位，以识别要出列的分组。

公开(公告)号：US07325099B2

公开(公告)日：2008-01-29

申请号：US10974122

申请日：2004-10-27

申请人： Sanjeev Jain ,  Mark B. Rosenbluth ,  Matthew Adiletta ,  Gilbert Wolrich

发明人： Sanjeev Jain ,  Mark B. Rosenbluth ,  Matthew Adiletta ,  Gilbert Wolrich

IPC分类号： G06F12/00

CPC分类号： H04L12/2854 ,  G06F12/0862 ,  G06F12/0875

摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.

摘要翻译： 实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。 用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。 在一个实施例中，DRAM包括双数据速率（DDR）DRAM。 公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。 该架构还包括用于执行各种分组处理功能的多个计算引擎。 一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。 随后，一个或多个分组处理功能可以通过从高速缓存访​​问功能元数据来操作。 功能完成后，将功能元数据写回到基于DRAM的商店。 该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

公开(公告)号：US20060159103A1

公开(公告)日：2006-07-20

申请号：US11026652

申请日：2004-12-30

申请人： Sanjeev Jain ,  Donald Hooper

发明人： Sanjeev Jain ,  Donald Hooper

IPC分类号： G06F15/16 ,  H04L12/56

CPC分类号： G06F12/0815 ,  H04L47/50

摘要： In general, in one aspect, the disclosure describes a method that includes at a first packet processing thread executing at a first core, performing a memory read to data shared between packet processing threads including the first thread. The method also includes at the first packet processing thread, determining whether the data returned by the memory read has been changed by a packet processing thread operating on another core before performing an exclusive operation on the shared data by the first packet processing thread.

公开(公告)号：US20060153185A1

公开(公告)日：2006-07-13

申请号：US11026449

申请日：2004-12-28

申请人： Sanjeev Jain ,  Mark Rosenbluth

发明人： Sanjeev Jain ,  Mark Rosenbluth

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L49/9047 ,  H04L49/90 ,  H04L49/9031

摘要： Systems and methods for dynamically changing ring size in network processing are disclosed. In one embodiment, a method generally includes requesting a free memory block from a free block pool manager by a ring manager for a corresponding ring when a first memory block is filled, receiving an address of a free memory block from the free block pool manager in response to the request from the ring manager, storing the address of the free memory block in the first memory block by the ring manager, the storing linking the free memory block to the first memory block as a next linked memory block to the first memory block, and repeating the requesting, receiving and storing for each additional linked memory blocks. An external service thread may be assigned to fulfill block fill-up requests from the free block pool manager.

摘要翻译： 公开了用于在网络处理中动态改变环尺寸的系统和方法。 在一个实施例中，一种方法通常包括当填充第一存储器块时由环管理器从空闲块池管理器请求空闲存储器块，从空闲块池管理器接收空闲存储器块的地址 响应于来自环管理器的请求，环路管理器将空闲存储器块的地址存储在第一存储器块中，存储将空闲存储器块作为下一个链接的存储器块链接到第一存储器块 并且对于每个附加的链接的存储块重复请求，接收和存储。 可以分配外部服务线程以实现来自空闲块池管理器的块填充请求。