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公开(公告)号：US20080168333A1
公开(公告)日：2008-07-10
申请号：US11959551
申请日：2007-12-19
IPC分类号： H03M13/00
CPC分类号： H03M13/114 , H03M13/1111 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/2936 , H03M13/2948 , H03M13/3905 , H03M13/4146
摘要： A decoding method for sorting received words in the order of the magnitude of the reliability of the received words, performing belief propagation using a parity check matrix diagonalized in the order to update the reliabilities, and repetitively performing the sorting and the belief propagation for the updated values, includes an inner repeated decoding process step of performing belief propagation using a parity check matrix diagonalized in an order of columns corresponding to symbols having comparatively low reliability values of the received words to update the reliability and repetitively performing the belief propagation based on the updated reliability; the inner repeated decoding process step in the second or later cycle of repetition thereof including diagonalization of the parity check matrix for restricted ones of the columns of the parity check matrix.
摘要翻译： 一种用于按接收字的可靠性大小的顺序对接收到的字进行分类的解码方法，使用以对等化的奇偶校验矩阵来执行置信传播，以更新可靠性，并且重复地执行用于更新的可更新的排序和置信传播 值包括内部重复解码处理步骤，其使用对应于与所接收到的字的具有相对低的可靠性值的符号相对应的列的顺序对角化的奇偶校验矩阵来执行置信传播，以更新可靠性并基于更新后的重新执行置信传播 可靠性; 内部重复解码处理步骤在其重复的第二或更晚的循环中，包括奇偶校验矩阵的有限列的奇偶校验矩阵的对角化。
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公开(公告)号：US08489955B2
公开(公告)日：2013-07-16
申请号：US12743487
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
IPC分类号： H03M13/00
CPC分类号： H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/2703 , H03M13/2707 , H03M13/271 , H03M13/6552 , H03M13/6555 , H04L1/0057
摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.
摘要翻译： 本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。 当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理 使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织 存储器的每列的存储器方向。 本发明可以应用于例如用于发送LDPC码的发送装置。
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公开(公告)号：US08464122B2
公开(公告)日：2013-06-11
申请号：US12743398
申请日：2008-11-26
IPC分类号： H03M13/00
摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer 25 replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. For example, when m is 12 and b is 1, where the i+1th bits from the most significant bit of the 12×1 code bits and the 12×1 symbol bits of one symbol are represented as bits bi and yi, replacement for allocating, for example, b0 to y8, b1 to y0, b2 to y6, b3 to y1, b4 to y4, b5 to y5, b6 to y2, b7 to y3, b8 to y7, b9 to y10, b10 to y11 and b11 to y9 is carried out. The present invention can be applied, for example, to a transmission system for transmitting an LDPC code and so forth.
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14.发明授权Data processing apparatus and data processing method as well as encoding apparatus and encoding method 有权数据处理装置和数据处理方法以及编码装置和编码方法公开(公告)号：US08402337B2
公开(公告)日：2013-03-19
申请号：US12743649
申请日：2008-11-18
IPC分类号： G06F11/00
CPC分类号： H04L27/3416 , H03M13/036 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/356 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3488 , H04L27/36
摘要： A data processing apparatus, a data processing method, an encoding apparatus and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve the tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.
摘要翻译： 可以应用于例如用于发送LDPC码等的传输系统的数据处理装置，数据处理方法，编码装置和编码方法，并且可以提高对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和2/3的编码速率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。
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15.发明申请DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD 有权数据处理设备和数据处理方法，如编码设备和编码方法公开(公告)号：US20100275100A1
公开(公告)日：2010-10-28
申请号：US12743384
申请日：2008-11-25
CPC分类号： H04L27/3416 , H03M13/036 , H03M13/1165 , H03M13/255 , H03M13/271 , H03M13/356 , H03M13/6552 , H04L1/0057 , H04L1/0071 , H04L27/3488 , H04L27/36
摘要： A data processing apparatus, a data processing method, an encoding apparatus, and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by bi and yi, respectively, replacement of allocating b0 to y15, b1 to y7, b2 to y1, b3 to y5, b4 to y6, b5 to y13, b6 to y11, b7 to y9, b8 to y8, b9 to y14, b10 to y12, b11 to y3, b12 to y0, b13 to y10, b14 to y4 and b15 to y2.
摘要翻译： 可以应用于例如用于发送LDPC码的传输系统等的数据处理装置，数据处理方法，编码装置和编码方法，并且可以改善对误差的容限。 在DVB-S.2中规定的并且具有64,800的码长和2/3的编码速率的LDPC码中，替换mb个码比特，并且替换后的码比特成为b符号的符号比特。 当m为8且b为2时，分别用b 1和y i表示从8×2码位的最高有效位和2个连续符号的8×2符号位的第i + 1位，将b0分配给 y15，b1〜y7，b2〜y1，b3〜y5，b4〜y6，b5〜y13，b6〜y11，b7〜y9，b8〜y8，b9〜y14，b10〜y12，b11〜y3，b12〜y0， b13〜y10，b14〜y4，b15〜y2。
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公开(公告)号：US20090106622A1
公开(公告)日：2009-04-23
申请号：US12253347
申请日：2008-10-17
申请人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
发明人： Takashi Yokokawa , Satoshi Okada , Osamu Shinya
CPC分类号： H03M13/11 , H04L1/0052 , H04L1/0057 , H04L1/007
摘要： A receiving apparatus including, an LDPC decoder configured to decode both of the data signal and the transmission control signal, a data signal input buffer arranged before the LDPC decoder and configured to hold the received data signal and a transmission control signal input buffer arranged before the LDPC decoder and configured to hold the received transmission control signal, and a controller configured to select one of the data signal held in the data signal input buffer and the transmission control signal held in the transmission control signal input buffer as a signal subject to decoding and transmit the selected signal to the LDPC decoder to make the LDPC decoder decode the signal subject to decoding.
摘要翻译： 一种接收装置，包括：LDPC解码器，被配置为解码所述数据信号和所述传输控制信号;数据信号输入缓冲器，布置在所述LDPC解码器之前并被配置为保持所述接收的数据信号;以及传输控制信号输入缓冲器， LDPC解码器，被配置为保持所接收的发送控制信号，以及控制器，被配置为选择保持在数据信号输入缓冲器中的数据信号中的一个和保持在发送控制信号输入缓冲器中的发送控制信号作为经解码的信号;以及 将所选择的信号发送到LDPC解码器，以使LDPC解码器对经过解码的信号进行解码。
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公开(公告)号：US08774286B2
公开(公告)日：2014-07-08
申请号：US12851796
申请日：2010-08-06
申请人： Takashi Yokokawa , Satoshi Okada
发明人： Takashi Yokokawa , Satoshi Okada
CPC分类号： H04N21/4344 , H04N21/4345 , H04N21/4346 , H04N21/4347 , H04N21/6112
摘要： A receiving apparatus includes a buffer configured to store packets of a first packet sequence made up of packets extracted from one transport stream that are common to packets of another transport stream and packets of a second packet sequence made up of common packets, a read control section configured to read the packets of the first packet sequence and the second packet sequence stored in the buffer after the passing of a predetermined time after synchronization is established between the packets of the first packet sequence and the packets of the second packet sequence, thereby reconstructing one transport stream from the first packet sequence and the second packet sequence, and an output section configured to output the reconstructed transport stream.
摘要翻译： 接收装置包括：缓冲器，被配置为存储由从一个传输流提取的分组构成的第一分组序列的分组，所述分组对于另一个传输流的分组是公共的，以及由公共分组组成的第二分组序列的分组;读取控制部分 被配置为在第一分组序列的分组与第二分组序列的分组之间建立同步之后经过预定时间之后，读取存储在缓冲器中的第一分组序列和第二分组序列的分组，从而重新构建一个 从第一分组序列和第二分组序列传输流，以及输出部分，被配置为输出重构的传输流。
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公开(公告)号：US08520754B2
公开(公告)日：2013-08-27
申请号：US12958729
申请日：2010-12-02
申请人： Takashi Yokokawa , Satoshi Okada , Tomoharu Honda
发明人： Takashi Yokokawa , Satoshi Okada , Tomoharu Honda
IPC分类号： H04K1/10
CPC分类号： H04L27/2656 , H04H60/11 , H04L27/2602 , H04L27/2666 , H04N21/4382 , H04N21/6112
摘要： Disclosed herein is a reception apparatus, including: a reception section adapted to receive an OFDM (Orthogonal Frequency Division Multiplexing) signal obtained by modulating a first frame configured so as to include packets of a common packet sequence configured from a packet common to a plurality of streams and a second frame configured so as to include packets of a data packet sequence configured from packets individually unique to the plural streams; an acquisition section adapted to acquire specification information for specifying a combination of a first frame and a second frame obtained by demodulating the received OFDM signal; and a detection section adapted to detect a combination of a packet of the common packet sequence which configures the first frame and a packet of the data packet sequence which configures the second frame, whose combination is specified based on the acquired specification information.
摘要翻译： 这里公开了一种接收装置，包括：接收部分，适于接收通过调制第一帧而获得的OFDM（正交频分复用）信号，所述第一帧被配置为包括由公共数据包共同配置的公共分组序列的分组 流和第二帧，其被配置为包括由对于多个流单独唯一的分组配置的数据分组序列的分组; 获取部分，适于获取用于指定通过解调所接收的OFDM信号而获得的第一帧和第二帧的组合的指定信息; 以及检测部，其适于检测构成所述第一帧的公共分组序列的分组与构成所述第二帧的所述数据分组序列的分组的组合，所述组合基于所获取的规格信息来指定。
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公开(公告)号：US08176402B2
公开(公告)日：2012-05-08
申请号：US12110064
申请日：2008-04-25
IPC分类号： H03M13/00
CPC分类号： G06F11/1008 , G11B20/1833 , G11B20/1866
摘要： A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
摘要翻译： 解码装置包括存储器和接收单元，并且适于以包括奇偶校验部分的码字为单位对数据进行解码。 存储器具有能够存储长度等于一个码字的长度的至少数据的存储容量。 接收单元以比特交织形式接收码字的元素作为接收值，对接收到的值执行比特解交织和奇偶校验，并将所得到的接收值存储在存储器中。
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公开(公告)号：US20100281329A1
公开(公告)日：2010-11-04
申请号：US12743487
申请日：2008-11-26
申请人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
发明人： Takashi Yokokawa , Makiko Yamamoto , Satoshi Okada , Lui Sakai , Ryoji Ikegaya
CPC分类号： H03M13/1165 , H03M13/1185 , H03M13/255 , H03M13/2703 , H03M13/2707 , H03M13/271 , H03M13/6552 , H03M13/6555 , H04L1/0057
摘要： The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors.Where two or more bits of an LDPC (Low Density Parity Check) code are set as one symbol and are mapped to 214 or 216 signal points, a column twist interleaver 24 carries out, as a re-arrangement process for re-arranging code bits of an LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not included in one symbol, column twist interleave of changing the writing starting position when code bits are written in a column direction of a memory for each column of the memory. The present invention can be applied, for example, to a transmission apparatus for transmitting an LDPC code.
摘要翻译： 本发明涉及一种数据处理装置，数据处理方法和程序，其可以将LDPC码的码位的容限提高到错误。 当LDPC（低密度奇偶校验）码的两个或多个比特被设置为一个符号并被映射到214或216个信号点时，列扭曲交织器24执行用于重新排列码位的重新排列处理 使得与包括在奇偶校验矩阵的一个任意行中的值1相对应的多个码位不包括在一个符号中的LDPC码，当码位被写入列时改变写入起始位置的列扭曲交织 存储器的每列的存储器方向。 本发明可以应用于例如用于发送LDPC码的发送装置。
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