公开(公告)号：US20050077548A1

公开(公告)日：2005-04-14

申请号：US10968050

申请日：2004-10-20

申请人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

发明人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

IPC分类号： H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

公开(公告)号：US07217607B2

公开(公告)日：2007-05-15

申请号：US10968050

申请日：2004-10-20

申请人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

发明人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。

公开(公告)号：US20050186724A1

公开(公告)日：2005-08-25

申请号：US11111890

申请日：2005-04-22

申请人： Fumio Ootsuka ,  Satoshi Yamamoto ,  Satoshi Sakai

发明人： Fumio Ootsuka ,  Satoshi Yamamoto ,  Satoshi Sakai

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/51

CPC分类号： H01L21/28194 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and suicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.

摘要翻译： 在包含MIS晶体管的半导体集成电路器件中，使用一种方法来形成用于实现高速性能的电路和在同一衬底上获得高可靠性的电路，其中栅极绝缘膜由 高介电常数绝缘膜。 在该方法中，在逻辑区域和I / O区域中的MIS晶体管的扩散区域上去除高介电常数绝缘膜，并且在扩散区域的表面上形成低电阻的硅化物层。 另一方面，在存储区域中，在MIS晶体管的扩散区域上未形成硅化物层，并且扩散区域被高介电常数绝缘膜覆盖，从而防止在形成半导体衬底期间损坏半导体衬底 间隔物，硅化物层和接触孔。

公开(公告)号：US06660597B2

公开(公告)日：2003-12-09

申请号：US10288539

申请日：2002-11-06

申请人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

发明人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。

公开(公告)号：US07655993B2

公开(公告)日：2010-02-02

申请号：US11738741

申请日：2007-04-23

申请人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

发明人： Ryoichi Furukawa ,  Satoshi Sakai ,  Satoshi Yamamoto

IPC分类号： H01L21/336

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。

公开(公告)号：US06924237B2

公开(公告)日：2005-08-02

申请号：US10281189

申请日：2002-10-28

申请人： Fumio Ootsuka ,  Satoshi Yamamoto ,  Satoshi Sakai

发明人： Fumio Ootsuka ,  Satoshi Yamamoto ,  Satoshi Sakai

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L29/51 ,  H01L21/302

CPC分类号： H01L21/28194 ,  H01L21/28518 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and silicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.

摘要翻译： 在包含MIS晶体管的半导体集成电路器件中，使用一种方法来形成用于实现高速性能的电路和在同一衬底上获得高可靠性的电路，其中栅极绝缘膜由 高介电常数绝缘膜。 在该方法中，在逻辑区域和I / O区域中的MIS晶体管的扩散区域上去除高介电常数绝缘膜，并且在扩散区域的表面上形成低电阻的硅化物层。 另一方面，在存储区域中，在MIS晶体管的扩散区域上未形成硅化物层，并且扩散区域被高介电常数绝缘膜覆盖，从而防止在形成半导体衬底期间损坏半导体衬底 间隔物，硅化物层和接触孔。

公开(公告)号：US20070187764A1

公开(公告)日：2007-08-16

申请号：US11738741

申请日：2007-04-23

申请人： RYOICHI FURUKAWA ,  Satoshi Sakai ,  Satoshi Yamamoto

发明人： RYOICHI FURUKAWA ,  Satoshi Sakai ,  Satoshi Yamamoto

IPC分类号： H01L23/62

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28202 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7833

摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.

摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。

公开(公告)号：US11167637B2

公开(公告)日：2021-11-09

申请号：US14390693

申请日：2012-04-12

申请人： Satoshi Yamamoto ,  Chiaki Kataoka ,  Masaki Akagi

发明人： Satoshi Yamamoto ,  Chiaki Kataoka ,  Masaki Akagi

IPC分类号： B60K15/04

摘要： To obtain a fuel filler structure for a fuel tank wherein when causing an opening and closing valve to close, it can be ensured that the opening and closing valve does not rapidly rotate to a closed position in which it closes a fuel fill inlet, and when causing the opening and closing valve to open, the opening and closing valve can be opened with a small force. A fuel filler structure is equipped with a damper on the near side of a flapper valve in the insertion direction of a fuel nozzle. When the flapper valve rotates to an open position, the damper does not act on the flapper valve, and when the flapper valve rotates to a closed position, the damper acts on the flapper valve.

公开(公告)号：US10534236B2

公开(公告)日：2020-01-14

申请号：US15737115

申请日：2016-06-17

申请人： Satoshi Yamamoto ,  Daisuke Goto ,  Toshiya Sagisaka ,  Masato Shinoda ,  Mamiko Inoue ,  Fuminari Kaneko ,  Tohru Yashiro

发明人： Satoshi Yamamoto ,  Daisuke Goto ,  Toshiya Sagisaka ,  Masato Shinoda ,  Mamiko Inoue ,  Fuminari Kaneko ,  Tohru Yashiro

IPC分类号： G02F1/15 ,  C07D265/28 ,  G09F9/30 ,  C09K9/02 ,  C08F20/36 ,  C07D265/38 ,  G02F1/1516

摘要： Provided is an electrochromic compound represented by the following general formula (I) or (II) where R1 to R13 are each independently a hydrogen atom, a halogen atom, a monovalent organic group, or a polymerizable functional group, and at least one of the R1 to the R13 is a polymerizable functional group.

公开(公告)号：US09869918B2

公开(公告)日：2018-01-16

申请号：US14988992

申请日：2016-01-06

申请人： Takahiko Matsumoto ,  Keiichiroh Yutani ,  Hidekazu Yaginuma ,  Koh Fujimura ,  Fuminari Kaneko ,  Mamiko Inoue ,  Sukchan Kim ,  Satoshi Yamamoto ,  Tohru Yashiro

发明人： Takahiko Matsumoto ,  Keiichiroh Yutani ,  Hidekazu Yaginuma ,  Koh Fujimura ,  Fuminari Kaneko ,  Mamiko Inoue ,  Sukchan Kim ,  Satoshi Yamamoto ,  Tohru Yashiro

IPC分类号： G02F1/155 ,  G02F1/1343

CPC分类号： G02F1/155 ,  G02F1/13439 ,  G02F2001/1552

摘要： An electrochromic apparatus including a first support, a first electrode, a first transparent conductive layer, an electrochromic layer, a second support, a second electrode, a second transparent conductive layer, and an electrolyte layer is provided. The first and second supports have first and second surfaces, respectively, on each of which a plurality of grooves is formed. The grooves on the second surface are facing the grooves on the first surface. The first and second electrodes are disposed at each one of the plurality of grooves of the first and second supports, respectively. The first and second transparent conductive layers are in contact with the first and second surfaces, respectively. The electrochromic layer is in contact with the first transparent conductive layer. The electrolyte layer is between the electrochromic layer and the second transparent conductive layer.