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公开(公告)号：US06909133B2
公开(公告)日：2005-06-21
申请号：US10699690
申请日：2003-11-04
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L29/108
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28202 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。
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公开(公告)号：US20050077548A1
公开(公告)日：2005-04-14
申请号：US10968050
申请日：2004-10-20
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/78 , H01L23/62
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28202 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
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公开(公告)号：US07217607B2
公开(公告)日：2007-05-15
申请号：US10968050
申请日：2004-10-20
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28202 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。
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4.发明授权公开(公告)号：US07186604B2
公开(公告)日：2007-03-06
申请号：US10519799
申请日：2002-08-15
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/823857
摘要： After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.
摘要翻译： 在半导体衬底1的区域A的表面上形成氧化硅膜9之后，在半导体衬底1上依次沉积高介电常数绝缘膜10，硅膜，氧化硅膜14，并将其图案化 以将氧化硅膜14留在用于形成栅电极的区域中。 然后，通过使用图案化氧化硅膜14作为掩模来制造硅膜13 n和13 p之后，当去除氧化硅膜14时，在氧化硅膜14的蚀刻选择性高的条件下进行蚀刻 介电常数绝缘膜10变大，从而将高介电常数绝缘膜10也留在栅电极（13n，13p）的端部下方的部分。 因此，可以确保其耐受电压并改善MISFET的特性。
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公开(公告)号：US06660597B2
公开(公告)日：2003-12-09
申请号：US10288539
申请日：2002-11-06
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28202 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。
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公开(公告)号：US20070187764A1
公开(公告)日：2007-08-16
申请号：US11738741
申请日：2007-04-23
IPC分类号： H01L23/62
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28202 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。
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7.发明申请公开(公告)号：US20060121740A1
公开(公告)日：2006-06-08
申请号：US10519799
申请日：2002-08-15
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L29/513 , H01L21/823857
摘要： After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.
摘要翻译： 在半导体衬底1的区域A的表面上形成氧化硅膜9之后，在半导体衬底1上依次沉积高介电常数绝缘膜10，硅膜，氧化硅膜14，并将其图案化 以将氧化硅膜14留在用于形成栅电极的区域中。 然后，通过使用图案化氧化硅膜14作为掩模来制造硅膜13 n和13 p之后，当去除氧化硅膜14时，在氧化硅膜14的蚀刻选择性高的条件下进行蚀刻 介电常数绝缘膜10变大，从而将高介电常数绝缘膜10也留在栅电极（13n，13p）的端部下方的部分。 因此，可以确保其耐受电压并改善MISFET的特性。
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公开(公告)号：US07655993B2
公开(公告)日：2010-02-02
申请号：US11738741
申请日：2007-04-23
IPC分类号： H01L21/336
CPC分类号： H01L21/28194 , H01L21/28079 , H01L21/28202 , H01L21/823462 , H01L21/823842 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： In a process of forming MISFETs that have gate insulating films that are mutually different in thickness on the same substrate, the formation of an undesirable natural oxide film at the interface between the semiconductor substrate and the gate insulating film is suppressed. A gate insulating film of MISFETs constituting an internal circuit is comprised of a silicon oxynitride film. Another gate insulating film of MISFETs constituting an I/O circuit is comprised of a laminated silicon oxynitride film and a high dielectric film. A process of forming the two types of gate insulating films on the substrate is continuously carried out in a treatment apparatus of a multi-chamber system. Accordingly, the substrate will not be exposed to air. Therefore, it is possible to suppress the inclusion of undesirable foreign matter and the formation of a natural oxide film at the interface between the substrate and the gate insulating films.
摘要翻译： 在形成具有相同基板上的厚度相互不同的栅极绝缘膜的MISFET的过程中，抑制了在半导体基板和栅极绝缘膜之间的界面处形成不期望的自然氧化膜。 构成内部电路的MISFET的栅极绝缘膜由氮氧化硅膜构成。 构成I / O电路的MISFET的另一个栅极绝缘膜由层叠的氮氧化硅膜和高介电膜构成。 在多室系统的处理装置中连续地进行在基板上形成两种栅极绝缘膜的工序。 因此，基板不会暴露在空气中。 因此，可以抑制在基板和栅极绝缘膜之间的界面处包含不需要的异物和形成自然氧化膜。
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公开(公告)号：US07897467B2
公开(公告)日：2011-03-01
申请号：US12784876
申请日：2010-05-21
申请人： Satoshi Sakai , Atsushi Hiraiwa , Satoshi Yamamoto
发明人： Satoshi Sakai , Atsushi Hiraiwa , Satoshi Yamamoto
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823462 , H01L21/82345 , H01L21/823842 , H01L21/823857 , H01L21/823878
摘要： After silicon oxide film (9) is formed on the surface of a semiconductor substrate (1), the silicon oxide film (9) in a region in which a gate insulation film having a small effective thickness is formed is removed using diluted HF and after that, high dielectric constant insulation film (10) is formed on the semiconductor substrate (1). Consequently, two kinds of gate insulation films, namely, a gate insulation film (12) comprised of stacked film of high dielectric constant insulation film (10) and silicon oxide film (9) and gate insulation film (11) comprised of the high dielectric constant insulation film (10) are formed on the semiconductor substrate (1).
摘要翻译： 在半导体基板（1）的表面上形成氧化硅膜（9）之后，使用稀释的HF除去形成有效厚度小的栅极绝缘膜的区域中的氧化硅膜（9） 在半导体衬底（1）上形成高介电常数绝缘膜（10）。 因此，由高介电常数绝缘膜（10）和氧化硅膜（9）构成的栅极绝缘膜（12）和栅极绝缘膜（12）构成的两种栅极绝缘膜由高介电常数 在半导体衬底（1）上形成恒定绝缘膜（10）。
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公开(公告)号：US20050186724A1
公开(公告)日：2005-08-25
申请号：US11111890
申请日：2005-04-22
申请人： Fumio Ootsuka , Satoshi Yamamoto , Satoshi Sakai
发明人： Fumio Ootsuka , Satoshi Yamamoto , Satoshi Sakai
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/10 , H01L29/51
CPC分类号： H01L21/28194 , H01L21/28518 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and suicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.
摘要翻译： 在包含MIS晶体管的半导体集成电路器件中，使用一种方法来形成用于实现高速性能的电路和在同一衬底上获得高可靠性的电路，其中栅极绝缘膜由 高介电常数绝缘膜。 在该方法中，在逻辑区域和I / O区域中的MIS晶体管的扩散区域上去除高介电常数绝缘膜，并且在扩散区域的表面上形成低电阻的硅化物层。 另一方面，在存储区域中，在MIS晶体管的扩散区域上未形成硅化物层，并且扩散区域被高介电常数绝缘膜覆盖，从而防止在形成半导体衬底期间损坏半导体衬底 间隔物，硅化物层和接触孔。
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