公开(公告)号：US08032809B2

公开(公告)日：2011-10-04

申请号：US11721213

申请日：2005-12-06

申请人： Chan-ho Park ,  Kyoung Park ,  Myung-joon Kim

发明人： Chan-ho Park ,  Kyoung Park ,  Myung-joon Kim

IPC分类号： H04L1/18

CPC分类号： H04L69/16 ,  H04L1/1854 ,  H04L1/188 ,  H04L47/10 ,  H04L47/193 ,  H04L47/323 ,  H04L69/12 ,  H04L69/161 ,  H04L69/163

摘要： Provided is an apparatus for detection timeout of each channel, which is a socket connection, in a Transmission Control Protocol (TCP) Offload Engine (TOE) using TCP accelerating hardware, and a method thereof. The timer managing apparatus of the TOE using the TCP accelerating hardware, including: a command register for receiving a command for a retransmission timer or a delayed ACK timer from an embedded processor of the TOE; a finite state machine (FSM) for storing information of a timer in operation by analyzing the command for the retransmission timer or the delayed ACK timer stored in the command register and controlling an entire operation of the timer managing apparatus; and a timeout checker for checking timeout of a timer in operation by using the stored timer information and notifying the timeout to the FSM.

摘要翻译： 提供了一种使用TCP加速硬件的传输控制协议（TCP）卸载引擎（TOE）中的每个信道的检测超时的装置，其是套接字连接及其方法。 使用TCP加速硬件的TOE的定时器管理装置，包括：从TOE的嵌入式处理器接收重发定时器的命令或延迟的ACK定时器的命令寄存器; 用于通过分析存储在命令寄存器中的重传定时器或延迟ACK定时器的命令来存储定时器的操作信息的有限状态机（FSM），并控制定时器管理装置的整个操作; 以及一个超时检查器，用于通过使用存储的定时器信息来检查正在运行的定时器的超时并通知超时给FSM。

公开(公告)号：US06215167B1

公开(公告)日：2001-04-10

申请号：US09081832

申请日：1998-05-19

申请人： Chan-ho Park

发明人： Chan-ho Park

IPC分类号： H01L2358

CPC分类号： H01L29/7393 ,  H01L23/585 ,  H01L29/0615 ,  H01L29/402 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device having an breakdown voltage improving structure and a manufacturing method thereof are provided. A collector region and a base region create a pn junction between them. At least one accelerating region of the same conductivity type as the collector region is formed spaced from the pn junction and at a dose higher than that of the collector region. A field plate overlaps the pn junction and the accelerating region. The field plate has an edge portion that extends past the accelerating region. When a voltage of a reverse direction is applied to the pn junction, an electric field becomes concentrated on the accelerating region as well as on the pn junction and on the edge portion of the field plate. This increases an electric field distribution area and thus also increases the breakdown voltage.

摘要翻译： 提供具有击穿电压改善结构的功率半导体器件及其制造方法。 集电极区域和基极区域之间形成一个pn结。 至少一个与集电极区相同的导电类型的加速区域与pn结隔开并以比集电极区域更高的剂量形成。 场板与pn结和加速区重叠。 场板具有延伸超过加速区域的边缘部分。 当向pn结施加反向电压时，电场在加速区以及pn结和场板的边缘部分集中。 这增加了电场分布面积，从而也增加了击穿电压。

公开(公告)号：US6040219A

公开(公告)日：2000-03-21

申请号：US150171

申请日：1998-09-09

申请人： Chan-ho Park ,  Jae-hong Park

发明人： Chan-ho Park ,  Jae-hong Park

IPC分类号： H01L21/28 ,  H01L21/306 ,  H01L21/329 ,  H01L21/331 ,  H01L29/06 ,  H01L29/40 ,  H01L29/73 ,  H01L29/732 ,  H01L21/336

CPC分类号： H01L29/405 ,  H01L29/66136 ,  H01L29/66295

摘要： A method for manufacturing a power semiconductor device including a semi-insulating polycrystalline silicon (SIPOS) film is provided. According to this method, first, a conductive collector region is formed in a semiconductor substrate. Then, a first insulating film, which exposes a portion of the semiconductor substrate in which a base region is to be formed, is formed on said semiconductor substrate in which the collector region is formed. A conductive base region is formed in the collector region. A second insulating film is formed over the entire surface of the semiconductor substrate. After exposing a portion of the semiconductor substrate in which an emitter region and a channel stop region are to be formed, impurities for the emitter region are implanted into the base region. Simultaneously, a third insulating film is formed over the entire surface of the semiconductor substrate, while a conductive emitter region is formed by diffusing the impurities. At least one of the first to third insulating films is left only in a field region between the base region and the channel stop region. Parts of the base region, the emitter region, and the channel stop region are exposed after forming a semi-insulating polycrystalline silicon (SIPOS) film on the entire surface of the resultant structure. A base electrode, an emitter electrode, and an equipotential metal ring are then formed, respectively contacting the base region, the emitter region, and the channel stop region.

摘要翻译： 提供一种用于制造包括半绝缘多晶硅（SIPOS）膜的功率半导体器件的方法。 根据该方法，首先，在半导体衬底中形成导电性集电极区域。 然后，在形成集电极区域的所述半导体基板上形成露出要形成有基极区域的半导体衬底的一部分的第一绝缘膜。 在集电区域形成导电基区。 在半导体基板的整个表面上形成第二绝缘膜。 在将要形成发射极区域和沟道停止区域的半导体衬底的一部分暴露之后，将发射极区域的杂质注入基极区域。 同时，在半导体衬底的整个表面上形成第三绝缘膜，同时通过扩散杂质形成导电发射极区域。 第一至第三绝缘膜中的至少一个绝缘膜仅留在基极区域和沟道停止区域之间的场区域中。 在所得结构的整个表面上形成半绝缘多晶硅（SIPOS）膜之后，露出基极区域，发射极区域和沟道停止区域的部分。 然后形成分别接触基极区域，发射极区域和沟道停止区域的基极，发射极和等电位金属环。