公开(公告)号：US20200006612A1

公开(公告)日：2020-01-02

申请号：US16453332

申请日：2019-06-26

Applicant: SEOUL VIOSYS CO., LTD.

Inventor： Jin Woong LEE ,  Kyoung Wan KIM ,  Keum Ju LEE

IPC: H01L33/62 ,  H01L33/24 ,  H01L33/42 ,  H01L33/46

Abstract: A light emitting diode chip includes: a first conductivity type semiconductor layer; a mesa disposed on a partial region of the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; a transparent electrode being in ohmic contact with the second conductivity type semiconductor layer; a first current spreader being in ohmic contact with the first conductivity type semiconductor layer; a second current spreader electrically connected to the transparent electrode; an insulation layer covering the mesa, the first current spreader and the second current spreader, and including a distributed Bragg reflector. A lateral distance between the first current spreader and the mesa is larger than a thickness of the insulation layer, and a first side surface of the first current spreader close to the mesa is longer than the second side surface thereof.

公开(公告)号：US20150311390A1

公开(公告)日：2015-10-29

申请号：US14795167

申请日：2015-07-09

Applicant: Seoul Viosys Co., Ltd.

Inventor： Kyung Wan KIM ,  Tae Kyoon KIM ,  Yeo Jin YOON ,  Ye Seul KIM ,  Sang Hyun OH ,  Jin Woong LEE ,  In Soo KIM

IPC: H01L33/22 ,  H01L33/00

CPC classification number: H01L33/385 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/025 ,  H01L33/06 ,  H01L33/20 ,  H01L33/22 ,  H01L33/30 ,  H01L33/32 ,  H01L2933/0016 ,  H01L2933/0058

Abstract: A method of fabricating a light emitting diode (LED) includes: sequentially stacking a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a substrate; and separating the substrate into unit chips, and at the same time, forming a concavo-convex structure having the shape of irregular vertical lines in a side surface of the unit chip.

Abstract translation: 一种制造发光二极管（LED）的方法包括：在衬底上依次堆叠第一导电类型半导体层，有源层和第二导电类型半导体层; 并将基板分离为单元芯片，同时在单元芯片的侧面形成具有不规则垂直线形状的凹凸结构。