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    DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS
    11.
    发明申请
    DYNAMIC CRITICAL PATH DETECTOR FOR DIGITAL LOGIC CIRCUIT PATHS 有权
    DIGITAL LOGIC CIRCUIT PATHS的动态关键路径探测器

    公开(公告)号：US20090044160A1

    公开(公告)日：2009-02-12

    申请号：US11937111

    申请日：2007-11-08

    申请人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Peter A. Sandon ,  Peter A. Twombly ,  Charles S. Woodruff

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.

    摘要翻译： 用于校正集成电路中的定时故障的方法和用于监视集成电路的装置。 该方法包括将第一和第二闩锁放置在关键路径附近。 第一锁存器具有包括关键路径上的数据值的输入。 该方法还包括从数据值产生延迟的数据值，将延迟的数据值锁存在第二锁存器中，将数据值与延迟的数据值进行比较，以确定关键路径是否包括定时失败状态，以及执行预定的校正 衡量关键路径。 本发明还涉及电路所在的设计结构。

    Structure for task based debugger (transaction-event-job-trigger)
    12.
    发明授权
    Structure for task based debugger (transaction-event-job-trigger) 失效
    基于任务的调试器的结构（事务事件 - 作业触发）

    公开(公告)号：US07823017B2

    公开(公告)日：2010-10-26

    申请号：US12050982

    申请日：2008-03-19

    申请人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Charles S. Woodruff

    发明人： Serafino Bueti ,  Kenneth J. Goodnow ,  Todd E. Leonard ,  Gregory J. Mann ,  Charles S. Woodruff

    IPC分类号： G06F11/00

    CPC分类号： G06F17/5022 ,  G06F2217/14

    摘要： Disclosed is a design structure for an apparatus for a task based debugger (transaction-event-job-trigger). More specifically, an integrated event monitor for a SOC comprises functional cores each having a functional debug logic element. The cores are connected to an interconnect structure that links the functional debug logic elements. Each functional debug logic element is specifically dedicated to a function of its corresponding core, wherein the functional debug logic elements generate a table of function-specific system events. The system events are function-specific with respect to an associated core, wherein the system events include transaction events, controller events, processor events, interconnect structure arbiter events, interconnect interface core events, high speed serial link core events, and/or codec events.

    摘要翻译： 公开了用于基于任务的调试器（事务 - 事件 - 作业触发）的装置的设计结构。 更具体地，SOC的集成事件监视器包括各自具有功能调试逻辑元件的功能核心。 核心连接到链接功能调试逻辑元件的互连结构。 每个功能调试逻辑元件专门用于其相应核心的功能，其中功能调试逻辑元件产生功能特定系统事件表。 系统事件相对于相关联的核心是特定于功能的，其中系统事件包括交易事件，控制器事件，处理器事件，互连结构仲裁器事件，互连接口核心事件，高速串行链路核心事件和/或编解码器事件 。

    System and method for system-on-chip interconnect verification
    14.
    发明申请
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US20080215945A1

    公开(公告)日：2008-09-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/3177 ,  G06F13/00 ,  G06F11/25

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    System and method for system-on-chip interconnect verification
    16.
    发明授权
    System and method for system-on-chip interconnect verification 失效
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07313738B2

    公开(公告)日：2007-12-25

    申请号：US10906388

    申请日：2005-02-17

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    System and method for system-on-chip interconnect verification
    17.
    发明授权
    System and method for system-on-chip interconnect verification 有权
    系统级芯片互连验证的系统和方法

    公开(公告)号：US07865789B2

    公开(公告)日：2011-01-04

    申请号：US11819748

    申请日：2007-06-28

    申请人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam Courchesne ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01R31/28

    CPC分类号： G06F11/261 ,  G01R31/31717 ,  G01R31/318513 ,  G06F11/2236 ,  G06F17/5022

    摘要： A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

    摘要翻译： 一种用于验证片上系统互连的系统和方法包括：第一线性反馈移位寄存器，其耦合到第一片上系统分量的输出接口;第二线性反馈移位寄存器，其在第二片上系统组件 以及耦合到第二线性反馈移位寄存器和第二片上系统的输入接口的比较器。 另一种验证方法包括使用第一线性反馈移位寄存器和第二线性反馈移位寄存器使用相同的第一初始状态来产生伪随机数序列，并且将第一线性反馈移位寄存器的输出与第二线性反馈移位寄存器的输出进行比较 线性反馈移位寄存器和报告错误比较。

    Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry
    18.
    发明授权
    Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry 失效
    使用用于选定的电路块的预制和预合格曝光掩模来制造集成电路的方法

    公开(公告)号：US07519941B2

    公开(公告)日：2009-04-14

    申请号：US11279666

    申请日：2006-04-13

    申请人： Serafino Bueti ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman

    发明人： Serafino Bueti ,  Kenneth J. Goodnow ,  Gregory J. Mann ,  Jason M. Norman

    IPC分类号： G07F17/50

    CPC分类号： G03F1/84

    摘要： Disclosed are embodiments of a manufacturing method that establishes a library of pre-made and pre-qualified masks for patterning different blocks of circuitry that meet established performance and timing requirements. The embodiments of the method use stepped exposures of multiple masks, including at least one mask selected from this library, to pattern a chip design onto a silicon wafer, where the chip design is made up of two or more interconnected blocks of circuitry. Consequently, for a given integrated circuit design, pre-made/pre-qualified mask(s) can be selected from the library to pattern one, some or all blocks of circuitry for the design. Optionally, additional masks can be specially made and qualified to pattern other block(s) of circuitry (e.g., application specific logic) within the design. The blocks of circuitry patterned in this manner can be electrically connected via generic or customized interfaces in order to complete the chip design.

    摘要翻译： 公开了一种制造方法的实施例，其建立用于图案化满足已确定的性能和时序要求的不同电路块的预制和预先限定的掩模库。 该方法的实施例使用多个掩模的步进曝光，包括从该库选择的至少一个掩模，以将芯片设计图案化到硅晶片上，其中芯片设计由两个或更多个互连的电路块组成。 因此，对于给定的集成电路设计，可以从库中选择预制/预先限定的掩模，以对设计的一个，一些或所有电路块进行图案化。 可选地，附加掩模可以被特别地制造并且被限定以在设计中对其他电路块（例如，应用专用逻辑）进行图案化。 以这种方式图案化的电路块可通过通用或定制界面电连接，以完成芯片设计。

    Method and apparatus for monitoring integrated circuit temperature through deterministic path delays
    19.
    发明授权
    Method and apparatus for monitoring integrated circuit temperature through deterministic path delays 失效
    通过确定性路径延迟监测集成电路温度的方法和装置

    公开(公告)号：US07275011B2

    公开(公告)日：2007-09-25

    申请号：US11160601

    申请日：2005-06-30

    申请人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    发明人： Serafino Bueti ,  Adam J. Courchesne ,  Kenneth J. Goodnow ,  Jason M. Norman ,  Stanley B. Stanski ,  Scott T. Vento

    IPC分类号： G01K7/01

    CPC分类号： G01K3/14 ,  G01K3/10

    摘要： An apparatus for monitoring the temperature of an integrated circuit device includes a conductive wiring pattern formed on the integrated circuit device, extending into areas of the device to be monitored. A deterministic signal source is configured to generate a deterministic signal along the conductive wiring pattern, with one or more return paths tapped from selected locations along the pattern. A temperature change determination circuit is coupled to the one or more return paths and to a reference signal taken from the deterministic signal source. The circuit is configured to determine a delay between the reference signal and a delay signal traveling through at least a portion of the wiring pattern and a corresponding one of the return paths.

    摘要翻译： 用于监测集成电路器件的温度的装置包括形成在集成电路器件上的导电布线图形，延伸到待监视器件的区域中。 确定性信号源被配置为沿着导电布线图形生成确定性信号，其中从沿着图案的选定位置抽头的一个或多个返回路径。 温度变化确定电路耦合到一个或多个返回路径以及从确定性信号源获取的参考信号。 该电路被配置为确定参考信号和穿过布线图案的至少一部分和相应的一个返回路径的延迟信号之间的延迟。