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    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME
    11.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND METHOD FOR MANUFACTURING SAME 有权

    公开(公告)号：US20220005839A1

    公开(公告)日：2022-01-06

    申请号：US17364939

    申请日：2021-07-01

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tetsuo KIKUCHI

    IPC: H01L27/12

    Abstract: An active matrix substrate includes a first TFT and a second TFT, each of TFTs includes an oxide semiconductor layer and a gate electrode arranged on the oxide semiconductor layer with a gate insulating layer therebetween, in which in the first TFT, in the oxide semiconductor layer, in at least a part of a first region covered with the gate electrode with the gate insulating layer interposed therebetween, a layered structure including a high mobility oxide semiconductor film having a relatively high mobility and a low mobility oxide semiconductor film placed on the high mobility oxide semiconductor film and having a lower mobility than the high mobility oxide semiconductor film is provided, and in the second TFT, in a first region of the oxide semiconductor layer, throughout, of the high mobility oxide semiconductor film and the low mobility oxide semiconductor film, one oxide semiconductor film is provided, and the other oxide semiconductor film is not provided.

    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE
    12.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE 有权

    公开(公告)号：US20210273107A1

    公开(公告)日：2021-09-02

    申请号：US17183411

    申请日：2021-02-24

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Kengo HARA ,  Hitoshi TAKAHATA

    IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/49 ,  G02F1/1368

    Abstract: An active matrix substrate has pixel regions, and includes a substrate, pixel TFTs disposed to respectively correspond to the pixel regions, and pixel electrodes electrically connected to the pixel TFTs. The pixel TFTs are each a top gate structure TFT that has an oxide semiconductor layer, a gate insulating layer on the oxide semiconductor layer, and a gate electrode opposing the oxide semiconductor layer with the gate insulating layer therebetween. The gate insulating layer is formed of silicon oxide and includes a lower layer contacting the oxide semiconductor layer, and an upper layer on the lower layer. The lower layer H/N ratio of hydrogen atoms to nitrogen atoms in the lower layer is 1.5 to 5.0. The upper layer H/N ratio of hydrogen atoms to nitrogen atoms in the upper layer is 0.9 to 2.0. The lower layer H/N ratio is larger than the upper layer H/N ratio.

    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
    13.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME 有权

    公开(公告)号：US20210036158A1

    公开(公告)日：2021-02-04

    申请号：US16493803

    申请日：2018-03-08

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Setsuji NISHIMIYA ,  Tohru DAITOH ,  Masahiko SUZUKI ,  Kengo HARA ,  Hajime IMAI ,  Toshikatsu ITOH ,  Hideki KITAGAWA ,  Tetsuo KIKUCHI ,  Teruyuki UEDA

    IPC: H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L21/477 ,  H01L21/467 ,  H01L29/66

    Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semi-conductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.

    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 审中-公开

    公开(公告)号：US20200287054A1

    公开(公告)日：2020-09-10

    申请号：US16808463

    申请日：2020-03-04

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Masahiko SUZUKI ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Yoshimasa CHIKAMA ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA ,  Kengo HARA ,  Hitoshi TAKAHATA ,  Tohru DAITOH

    IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

    Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode that are electrically connected to the semiconductor layer, wherein the semiconductor layer has a stacked layer structure including a first oxide semiconductor layer including In, Ga, Zn, and Sn, and a second oxide semiconductor layer including In, Ga, Zn, and Sn, having a lower mobility than the first oxide semiconductor layer, and disposed on the first oxide semiconductor layer so as to be in direct contact with the first oxide semiconductor layer, the first and the second oxide semiconductor layers are amorphous, and a Sn atomic ratio R1 relative to all metal elements in the first oxide semiconductor layer and a Sn atomic ratio R2 relative to all metal elements in the second oxide semiconductor layer satisfy 0.8×R1≤R2≤1.2×R1.

    ACTIVE MATRIX SUBSTRATE AND PRODUCTION METHOD THEREFOR
    15.
    发明申请
    ACTIVE MATRIX SUBSTRATE AND PRODUCTION METHOD THEREFOR 审中-公开

    公开(公告)号：US20200185425A1

    公开(公告)日：2020-06-11

    申请号：US16613873

    申请日：2018-05-11

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Hideki KITAGAWA ,  Teruyuki UEDA ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Toshikatsu ITOH

    IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343

    Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interposed therebetween, and includes a portion that extends so as to overlap with the one of the plurality of gate bus lines.

    ACTIVE MATRIX SUBSTRATE
    16.
    发明申请
    ACTIVE MATRIX SUBSTRATE 审中-公开

    公开(公告)号：US20200183208A1

    公开(公告)日：2020-06-11

    申请号：US16084570

    申请日：2017-03-13

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Tetsuo KIKUCHI ,  Tohru DAITOH ,  Hajime IMAI ,  Toshikatsu ITOH ,  Hisao OCHI ,  Hideki KITAGAWA ,  Masahiko SUZUKI ,  Teruyuki UEDA ,  Ryosuke GUNJI ,  Kengo HARA ,  Setsuji NISHIMIYA

    IPC: G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362

    Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

    THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF PRODUCING THIN FILM TRANSISTOR SUBSTRATE
    19.
    发明申请
    THIN FILM TRANSISTOR SUBSTRATE AND METHOD OF PRODUCING THIN FILM TRANSISTOR SUBSTRATE 审中-公开

    公开(公告)号：US20200035717A1

    公开(公告)日：2020-01-30

    申请号：US16508603

    申请日：2019-07-11

    Applicant: Sharp Kabushiki Kaisha

    Inventor： Kengo HARA ,  Tohru DAITOH ,  Hajime IMAI ,  Tetsuo KIKUCHI ,  Masahiko SUZUKI ,  Setsuji NISHIMIYA ,  Teruyuki UEDA ,  Masamitsu YAMANAKA

    IPC: H01L27/12 ,  H01L29/786

    Abstract: A thin film transistor substrate includes a source line, a gate electrode, a channel region, a source region, a drain region, and a pixel electrode. The gate electrode is a portion of a first metal film disposed upper than a first insulating film that is disposed upper than a semiconductor film. The source line is a portion of a second metal film disposed upper than a second insulating film that is disposed upper than the first metal film. The channel region is a portion of a section of the semiconductor film and disposed to overlap the gate electrode. The source region is prepared by reducing a resistance of a section of the semiconductor film. The drain region is prepared by reducing a resistance of a section of the semiconductor film. The pixel electrode is prepared by reducing a resistance of a section of the semiconductor film.

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