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11.发明授权Method and device for forecasting/detecting polishing end point and method and device for monitoring real-time film thickness 失效用于预测/检测抛光终点的方法和装置以及用于监控实时胶片厚度的方法和装置公开(公告)号：US07821257B2
公开(公告)日：2010-10-26
申请号：US12228945
申请日：2008-08-18
申请人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
发明人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
CPC分类号： B24B37/013
摘要： A method and device for forecasting/detecting a polishing end point and for monitoring a real-time film thickness to suppress Joule heat loss due to the eddy current to the minimum, to precisely forecast/detect a polishing end point, to precisely calculate the remaining film thickness to be removed, and polishing rate. An inductor 36 in a sensor is arranged adjacent to a predetermined conductive film 28, and a magnetic flux change induced in the conductive film 28 by a magnetic flux formed by the inductor 36 is monitored, and by use of a magnetic flux change when a film thickness becomes corresponding to skin depth in which a film thickness in polishing is determined by the material of the predetermined conductive film 28 as a factor, a magnetic flux change part to forecast a polishing end point in the magnetic flux change process is detected, and a polishing end point is forecasted from the magnetic flux change part, and a polishing rate and a remaining film thickness amount to be removed are calculated on the spot.
摘要翻译： 一种用于预测/检测抛光终点并用于监测实时膜厚度以将由于涡流引起的焦耳热损失抑制到最小以精确地预测/检测抛光终点的方法和装置，以精确地计算剩余的 要去除的膜厚度和抛光速率。 传感器中的电感器36布置成与预定的导电膜28相邻，并且通过由电感器36形成的磁通量在导电膜28中感应的磁通量变化被监测，并且通过使用磁通量改变膜 厚度对应于其中通过预定导电膜28的材料确定抛光中的膜厚度的皮肤深度，检测用于预测磁通量变化过程中的抛光终点的磁通量变化部分，并且 从磁通量变化部分预测抛光终点，并且现场计算抛光速率和待除去的剩余膜厚度量。
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12.发明申请Polishing condition control apparatus and polishing condition control method of CMP apparatus 审中-公开抛光条件控制装置和CMP装置的抛光条件控制方法公开(公告)号：US20080268751A1
公开(公告)日：2008-10-30
申请号：US12082366
申请日：2008-04-10
IPC分类号： B24B49/02
CPC分类号： B24B37/005 , B24B49/12 , B24B51/00
摘要： To eliminate the unevenness of the remaining film thickness of the wafers, and increase the polishing efficiency, reduce the running cost and enhance the yield. A CMP apparatus 1 is equipped with a polishing recipe preparing means 3 that prepares polishing conditions so that the polishing conditions such as polishing speed, polishing pressure, abrasive and the like for the wafers become optimal, a remaining film thickness forecasting means 4 that forecasts the remaining film thickness of the wafer to be polished under the polishing conditions after polishing, a remaining film thickness measuring apparatus 4 that measures the remaining film thickness of the wafer after the polishing, and a computer 6 that controls the polishing conditions on the basis of the measurement results of the remaining film thickness. Further, the computer 6 includes a calculating unit 11 that calculate the difference between the measured value of the remaining film thickness and the forecasted value thereof, and a polishing condition correcting/changing unit 13 that corrects/changes the polishing conditions so that the calculated difference becomes minimal, and thereby, the correction/change of the polishing conditions is carried out in real time.
摘要翻译： 为了消除晶片的剩余膜厚度的不均匀性，提高研磨效率，降低运行成本，提高成品率。 CMP装置1配备有抛光配方准备装置3，其准备抛光条件，使得用于晶片的抛光速度，抛光压力，研磨剂等的抛光条件变得最佳;剩余膜厚度预测装置4，其预测 在研磨后的抛光条件下待研磨晶片的剩余膜厚度，测量抛光后晶片剩余膜厚度的剩余膜厚度测量装置4以及基于该抛光条件控制抛光条件的计算机6 剩余膜厚的测量结果。 此外，计算机6包括：计算剩余膜厚度的测量值与其预测值之间的差的计算单元11以及修正/改变抛光条件的抛光条件校正/改变单元13，使得计算出的差值 变得最小，从而实时地进行抛光条件的校正/变更。
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公开(公告)号：US07281136B2
公开(公告)日：2007-10-09
申请号：US09779440
申请日：2001-02-09
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
摘要翻译： 在LSI设计中采用加密处理，以便改进电路设计数据对传统示例的保密性。 在加密过程中，机密电路设计数据被加密以产生加密设计数据和加密密钥。 将加密的设计数据提供给进行设计/验证处理的用户。 钥匙也按要求提供。 在设计/验证过程中，对加密设计数据进行各种处理，而不会公开原始电路的内容。 在解码处理中，经受设计/验证处理的加密设计数据被解码以产生原始电路设计数据。
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公开(公告)号：US06886150B2
公开(公告)日：2005-04-26
申请号：US10067820
申请日：2002-02-08
CPC分类号： G06F17/5045
摘要： Information about an exclusive operation among a plurality of blocks and interconnection information about a sharable resource within each of these blocks are defined. Based on the sharable resource information and the inter-block exclusive operation information, a resource sharable among the blocks is extracted. Module specifications, in which information about interfaces, power dissipation, operation models and top-level hierarchy interconnection is stored, exclusive operation information describing an exclusive operation rule among the blocks, and prioritized function information used for preventing respective functions from being enabled at the same time are input to an generator, which is an automatic generating tool. In this manner, a power and clock management module for use in power save management, a wrapper bank select module storing interconnection information, a shared resource module storing information about a sharable resource and an optimized top-level hierarchy module storing interconnection information about an optimized top-level hierarchy are generated. Downsizing and power saving are realized by resource sharing and power management.
摘要翻译： 关于多个块中的排他性操作的信息和关于每个这些块内的可共享资源的互连信息被定义。 基于可共享资源信息和块间专用操作信息，提取在块之间可共享的资源。 存储关于接口，功耗，操作模型和顶级层级互连的信息的模块规格，描述块之间的排他性操作规则的排他性操作信息，以及用于防止各功能在相同功能中被使能的优先功能信息 时间被输入到作为自动生成工具的发电机。 以这种方式，用于节电管理的电源和时钟管理模块，存储互连信息的封装器组选择模块，存储关于可共享资源的信息的共享资源模块和存储关于优化的互连信息的优化顶层层级模块 生成顶级层次结构。 资源共享和电源管理实现了小型化和省电化。
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15.发明授权公开(公告)号：US07795865B2
公开(公告)日：2010-09-14
申请号：US11975195
申请日：2007-10-18
申请人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
发明人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
CPC分类号： H01L22/26 , B24B37/013 , B24B49/04 , B24B49/105 , H01L21/3212 , H01L2924/0002 , H01L2924/00
摘要： A method and device for forecasting and detecting a polishing endpoint and real time film thickness monitoring capable of suppressing to a minimum Joule heat loss due to an eddy current, and precisely forecasting and detecting the polishing endpoint, and precisely calculating a remaining film amount to be removed and a polishing rate. A high frequency inductor sensor is positioned close to the conductive film, and monitors a flux change induced in the conductive film. When a film thickness becomes a film thickness corresponding to a skin depth of the conductive film a method of calculating on the spot a polishing rate and a remaining film amount to be removed is provided.
摘要翻译： 一种用于预测和检测抛光终点和实时膜厚监测的方法和装置，其能够抑制由于涡流引起的最小焦耳热损失，并精确地预测和检测抛光终点，并精确计算剩余膜量 去除和抛光速率。 高频电感传感器位于靠近导电膜的位置，并监测导电膜中的磁通变化。 当膜厚成为与导电膜的皮肤深度相对应的膜厚时，提供了一种在现场计算抛光速率和待除去剩余膜量的方法。
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16.发明申请公开(公告)号：US20080290865A1
公开(公告)日：2008-11-27
申请号：US11975195
申请日：2007-10-18
申请人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
发明人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
IPC分类号： G01B7/06
CPC分类号： H01L22/26 , B24B37/013 , B24B49/04 , B24B49/105 , H01L21/3212 , H01L2924/0002 , H01L2924/00
摘要： An object of the present invention is to provide a method of forecasting and detecting a polishing endpoint and the device thereof and a real time film thickness monitoring method and the device thereof capable of suppressing a Joule heat loss to the minimum due to an eddy current, and precisely forecasting and detecting the polishing endpoint, and moreover, precisely calculating a remaining film amount to be removed and a polishing rate and the like on the spot so as to be able to accurately evaluate whether the predetermined conductive film is appropriately removed.To achieve the above described object, the present invention brings an inductor in a high frequency inductor type sensor close to the predetermined conductive film, and monitors a flux change induced in the predetermined conductive film by the flux formed by the inductor 36, and based on a flux change when a film thickness during the polishing becomes a film thickness corresponding to a skin depth decided with the material of the predetermined conductive film as a factor, detects a film thickness reference point, and forecasts the polishing endpoint from this film thickness reference point, and provides a method of calculating on the spot a polishing rate and a remaining film amount to be removed.
摘要翻译： 本发明的目的是提供一种预测和检测抛光终点及其装置的方法及其实时膜厚监测方法及其能够由于涡电流而将焦耳热损失抑制到最小的装置， 精确地预测和检测抛光终点，并且还准确地计算待去除的剩余膜量和现场抛光速率等，以便能够准确地评估预定导电膜是否被适当地去除。 为了实现上述目的，本发明使电感器在靠近预定导电膜的高频电感器型传感器中带动，并且通过由电感器36形成的磁通来监测在预定导电膜中感应的磁通量变化，并且基于 当抛光期间的膜厚度变为与由预定导电膜的材料确定的皮肤深度相对应的皮肤深度的膜厚度时的通量变化，检测膜厚度参考点，并且从该膜厚参考点预测抛光终点 ，并且提供一种现场计算要除去的抛光速率和剩余膜量的方法。
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公开(公告)号：US20080242197A1
公开(公告)日：2008-10-02
申请号：US12008350
申请日：2008-01-10
申请人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
发明人： Takashi Fujita , Toshiyuki Yokoyama , Keita Kitade
IPC分类号： B24B49/00
摘要： The present invention aims to provide a wafer polish monitoring method and device for detecting the end point of the polishing of a conductive film with high precision and accuracy by monitoring the variation of the film thickness of the conductive film without adverse influence of slurry or the like after the film thickness of the conductive film decreases to an extremely small film thickness defined by the skin depth. To achieve this objective, the present invention provides a wafer polish monitoring method by which a high-frequency transmission path is formed in a portion facing the conductive film on the surface of the wafer, the polishing removal state of the conductive film is evaluated based at least on the transmitted electromagnetic waves passing through the high-frequency transmission path or the reflected electromagnetic waves that are reflected without passing through the high-frequency transmission path, and the end point of the polishing removal and the point equivalent to the end point of the polishing removal are detected.
摘要翻译： 本发明的目的在于提供一种晶片抛光剂监测方法和装置，其通过监测导电膜的膜厚变化而不受浆料等的不利影响，高精度和高精度地检测导电膜的抛光终点 在导电膜的膜厚度降低到由皮肤深度限定的非常小的膜厚度之后。 为了达到上述目的，本发明提供了一种在晶片表面上与导电膜相对的部分形成高频传输路径的晶片抛光监视方法，基于 对穿过高频传输路径的透射电磁波或反射的电磁波至少不经过高频传输路径，抛光去除的终点和等同于 检测到抛光去除。
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公开(公告)号：US20070011468A1
公开(公告)日：2007-01-11
申请号：US11520712
申请日：2006-09-14
IPC分类号： G06F12/14
CPC分类号： G06F21/75 , G06F17/5022 , G06F21/6209
摘要： An encryption process is employed in the LSI design so as to improve confidentiality of the circuit design data over conventional examples. In the encryption process, confidential circuit design data is encrypted to produce encrypted design data and a cipher key. The encrypted design data is provided to the user who conducts a design/verification process. The key is also provided as required. In the design/verification process, the encrypted design data is subjected to various processes without disclosing the contents of the original circuit. In a decoding process, the encrypted design data subjected to the design/verification process is decoded to produce original circuit design data.
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公开(公告)号：US07148503B2
公开(公告)日：2006-12-12
申请号：US09968898
申请日：2001-10-03
CPC分类号： H01L23/5382 , G06F15/7867 , G06F17/5045 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/15192 , H01L2924/3011 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.
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公开(公告)号：US20060275932A1
公开(公告)日：2006-12-07
申请号：US11496574
申请日：2006-08-01
IPC分类号： H01L21/00
CPC分类号： H01L23/5382 , G06F15/7867 , G06F17/5045 , H01L23/544 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/15192 , H01L2924/3011 , Y02D10/12 , Y02D10/13 , H01L2924/00
摘要： The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs onto a silicon circuit board. The silicon circuit board includes a silicon substrate, a wiring layer and pads. IPs (chip IPs) are mounted onto the pads by lamination. Means for selecting, switching and setting the functions of the IPs are provided, making the semiconductor device suitable for small-variety mass-production.
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