公开(公告)号：US11861365B2

公开(公告)日：2024-01-02

申请号：US17306373

申请日：2021-05-03

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30145 ,  G06F9/3844

Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

公开(公告)号：US11797308B2

公开(公告)日：2023-10-24

申请号：US17718258

申请日：2022-04-11

Applicant: SiFive, Inc.

Inventor： Joshua Smith ,  Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/322 ,  G06F9/3844 ,  G06F9/3867

Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

公开(公告)号：US11556413B2

公开(公告)日：2023-01-17

申请号：US17115776

申请日：2020-12-08

Applicant: SiFive, Inc.

Inventor： Murali Vijayaraghavan ,  Krste Asanovic

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F9/30 ,  G06F12/1027 ,  G06F9/32

Abstract: Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

公开(公告)号：US20210173738A1

公开(公告)日：2021-06-10

申请号：US17115776

申请日：2020-12-08

Applicant: SiFive, Inc.

Inventor： Murali Vijayaraghavan ,  Krste Asanovic

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/1027 ,  G06F9/32 ,  G06F9/30

Abstract: Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

公开(公告)号：US20200210197A1

公开(公告)日：2020-07-02

申请号：US16362121

申请日：2019-03-22

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30

Abstract: Systems and methods are disclosed for secure predictors for speculative execution. Some implementations may eliminate or mitigate side-channel attacks, such as the Spectre-class of attacks, in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a predictor circuit that, when operating in a first mode, uses data stored in a set of predictor entries to generate predictions. For example, the integrated circuit may be configured to: detect a security domain transition for software being executed by the integrated circuit; responsive to the security domain transition, change a mode of the predictor circuit from the first mode to a second mode and invoke a reset of the set of predictor entries, wherein the second mode prevents the use of a first subset of the predictor entries of the set of predictor entries; and, after completion of the reset, change the mode back to the first mode.

公开(公告)号：US20190286443A1

公开(公告)日：2019-09-19

申请号：US16241455

申请日：2019-01-07

Applicant: SiFive, Inc.

Inventor： Alex Solomatnikov ,  Krste Asanovic

IPC: G06F9/30 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/355 ,  G06F9/50 ,  G06F12/02

Abstract: Systems and methods are disclosed for secure control flow prediction. Some implementations may be used to eliminate or mitigate the Spectre-class of attacks in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a control flow predictor with entries that include respective indications of whether the entry has been activated for use in a current process, wherein the integrated circuit is configured to access the indication in one of the entries that is associated with a control flow instruction that is scheduled for execution; determine, based on the indication, whether the entry of the control flow predictor associated with the control flow instruction is activated for use in a current process; and responsive to a determination that the entry is not activated for use in the current process, apply a constraint on speculative execution based on control flow prediction for the control flow instruction.

公开(公告)号：US12086067B2

公开(公告)日：2024-09-10

申请号：US18141463

申请日：2023-04-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F12/0855 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/0855 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0897

Abstract: Systems and methods are disclosed for load-store pipeline selection for vectors. For example, an integrated circuit (e.g., a processor) for executing instructions includes an L1 cache that provides an interface to a memory system; an L2 cache connected to the L1 cache that implements a cache coherency protocol with the L1 cache; a first store unit configured to write data to the memory system via the L1 cache; a second store unit configured to bypass the L1 cache and write data to the memory system via the L2 cache; and a store pipeline selection circuitry configured to: identify an address associated with a first beat of a store instruction with a vector argument; select between the first store unit and the second store unit based on the address associated with the first beat of the store instruction; and dispatch the store instruction to the selected store unit.

公开(公告)号：US11966290B2

公开(公告)日：2024-04-23

申请号：US18097252

申请日：2023-01-15

Applicant: SiFive, Inc.

Inventor： Murali Vijayaraghavan ,  Krste Asanovic

IPC: G06F11/10 ,  G06F9/30 ,  G06F9/32 ,  G06F11/07 ,  G06F11/30 ,  G06F12/1027

CPC classification number: G06F11/1068 ,  G06F9/30047 ,  G06F9/321 ,  G06F11/0772 ,  G06F11/3024 ,  G06F11/3037 ,  G06F12/1027

Abstract: Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.

公开(公告)号：US20240012948A1

公开(公告)日：2024-01-11

申请号：US18023948

申请日：2021-09-01

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F21/78

CPC classification number: G06F21/78

Abstract: Disclosed herein are systems and methods for processing masked memory accesses including handling fault exceptions and checking memory attributes of memory region(s) to be accessed. Implementations perform a two-level memory protection violation scheme for masked vector memory instructions. The first level memory check ignores mask information associated with a masked vector memory instruction and operates on a memory footprint associated with the masked vector memory instruction. If a memory protection violation is detected or speculative access is denied with respect to the memory footprint, a second level memory check evaluates mask information at a vector element level to determine whether a fault exception should be raised. If a mask bit for a vector element is set and a memory violation is detected, then a fault exception is raised for the masked vector memory instruction. If a mask bit is not set, execution of the masked vector memory instruction can continue.

公开(公告)号：US20230367715A1

公开(公告)日：2023-11-16

申请号：US18141463

申请日：2023-04-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F12/0855 ,  G06F12/0897 ,  G06F12/0815 ,  G06F12/0875

CPC classification number: G06F12/0855 ,  G06F12/0897 ,  G06F12/0815 ,  G06F12/0875

Abstract: Systems and methods are disclosed for load-store pipeline selection for vectors. For example, an integrated circuit (e.g., a processor) for executing instructions includes an L1 cache that provides an interface to a memory system; an L2 cache connected to the L1 cache that implements a cache coherency protocol with the L1 cache; a first store unit configured to write data to the memory system via the L1 cache; a second store unit configured to bypass the L1 cache and write data to the memory system via the L2 cache; and a store pipeline selection circuitry configured to: identify an address associated with a first beat of a store instruction with a vector argument; select between the first store unit and the second store unit based on the address associated with the first beat of the store instruction; and dispatch the store instruction to the selected store unit.