公开(公告)号：US20250110896A1

公开(公告)日：2025-04-03

申请号：US18979420

申请日：2024-12-12

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Terpstra

IPC: G06F12/14

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

公开(公告)号：US20240184721A1

公开(公告)日：2024-06-06

申请号：US18133022

申请日：2023-04-11

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook ,  Wesley Waylon Terpstra

IPC: G06F13/16

CPC classification number: G06F13/1626

Abstract: A method for managing orders of operations between one or more clients and one or more servers is disclosed. The method includes partitioning addressable regions of logical servers on or within an interconnect link into multiple regions including a first orderable region, and providing logical client an ability to push ordering responsibility within the first orderable region to a server. Over the first orderable region, two request messages for access to memory-mapped sources including two respective operations are transmitted, and the two request messages originate from a same logical client. The ordering responsibility can include a first rule for order of operations between the two request messages.

公开(公告)号：US20240184720A1

公开(公告)日：2024-06-06

申请号：US18341093

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F13/16 ,  G06F12/084 ,  G06F13/42

CPC classification number: G06F13/1621 ,  G06F12/084 ,  G06F13/4234

Abstract: First agent circuitry may receive from a second agent a first request and a first set of one or more bits. The first request may be part of a data operation. The first agent circuitry may transmit to the second agent a message including a first response to the first request, the first set of one or more bits, a second request, and a second set of one or more bits. The second set of one or more bits may be generated by the first agent circuitry to transmit state information about the second request. In some implementations, a set of one or more wires may be generated for transmission of the second set of one or more bits. The first agent circuitry may receive from the second agent a second response to the second request and the second set of one or more bits.

公开(公告)号：US20240184718A1

公开(公告)日：2024-06-06

申请号：US18132572

申请日：2023-04-10

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/14

CPC classification number: G06F12/1458 ,  G06F2212/1052

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

公开(公告)号：US20240184702A1

公开(公告)日：2024-06-06

申请号：US18182778

申请日：2023-03-13

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Michael Klinglesmith

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024

Abstract: Prefetch circuitry may be configured to transmit a message to prefetch one or more cache blocks of a group. The message may indicate an address for the group of cache blocks and a bit field that indicates the one or more cache blocks of the group to prefetch. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to prefetch the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.