公开(公告)号：US12248401B2

公开(公告)日：2025-03-11

申请号：US18341244

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/0831

Abstract: An agent may be configured to invoke a first eviction operation that is interruptible by probe operations when receiving a first type of eviction message and invoke a second eviction operation in which probe operations are interruptible by the second eviction operation when receiving a second type of eviction message. In some implementations, the agent may maintain a data storage that is inclusive of at least one of unique or dirty cache blocks in a cache maintained by an agent that transmits the second type of eviction message. In some implementations, the agent may prevent a cache block from transitioning from a modified state to an exclusive state when the agent invokes the second eviction operation to evict the cache block. In some implementations, the agent may convert from the second eviction operation to the first eviction operation when receiving the second type of eviction message.

公开(公告)号：US12197335B2

公开(公告)日：2025-01-14

申请号：US18182772

申请日：2023-03-13

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Michael Klinglesmith

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0897

Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.

公开(公告)号：US20240184725A1

公开(公告)日：2024-06-06

申请号：US18497436

申请日：2023-10-30

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F13/18 ,  G06F13/16

CPC classification number: G06F13/18 ,  G06F13/1678 ,  G06F13/1689

Abstract: A data responder may determine a selection between granting a request for a priority byte to be prioritized for transmission ahead of other bytes via a bus and ignoring the request. Granting the request may include transferring a block of bytes of data across multiple clock cycles with the priority byte transferred in a first clock cycle before other clock cycles of the multiple clock cycles. Ignoring the request may include transferring the block across multiple clock cycles with the priority byte transferred in a clock cycle after the first clock cycle. The data responder may receive the request from a data requestor. The data responder may assert a signal on a wire, connected to the data requestor, to indicate a grant of the request and a transfer of the priority byte in the first clock cycle.

公开(公告)号：US12204462B2

公开(公告)日：2025-01-21

申请号：US18132572

申请日：2023-04-10

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/14

Abstract: Cache circuitry may be configured to receive a first message to downgrade a permission associated with data stored in a current level cache. For example, the current level cache could be a level two (L2) cache. The cache circuitry could receive the first message from a processor core having a level one (L1) cache. The cache circuitry may forward the first message to a higher level cache. For example, the higher level cache could be a level three (L3) cache. The cache circuitry may downgrade the permission associated with data stored in the current level cache based on receiving a second message from the higher level cache. The cache circuitry may forward the first message before receiving the second message and downgrading the permission. The second message may cause downgrade of the permission in multiple caches (e.g., the L1, L2, and L3 caches).

公开(公告)号：US12189544B2

公开(公告)日：2025-01-07

申请号：US18341093

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F13/16 ,  G06F12/084 ,  G06F13/42

Abstract: First agent circuitry may receive from a second agent a first request and a first set of one or more bits. The first request may be part of a data operation. The first agent circuitry may transmit to the second agent a message including a first response to the first request, the first set of one or more bits, a second request, and a second set of one or more bits. The second set of one or more bits may be generated by the first agent circuitry to transmit state information about the second request. In some implementations, a set of one or more wires may be generated for transmission of the second set of one or more bits. The first agent circuitry may receive from the second agent a second response to the second request and the second set of one or more bits.

公开(公告)号：US20240370329A1

公开(公告)日：2024-11-07

申请号：US18142091

申请日：2023-05-02

Applicant: SiFive, Inc.

Inventor： Cameron Mcnairy ,  Michael Klinglesmith

IPC: G06F11/07

Abstract: A first circuitry may have a first interface. A response circuitry having a system interface may connect to the first circuitry. The response circuitry may receive an input selection that determines an error handling mode used to respond to an error (e.g., in a lockstep system, the error could be a difference between an output at the first interface and a second output at a second interface identified by comparing the first output to the second output). In some implementations, the error handling mode may cause the response circuitry to provide the output to the system interface and send an indication to software based on detecting the error. In some implementations, the error handling mode may cause the response circuitry to contain at least a portion of the output by disabling at least a portion of the system interface for multiple clock cycles based on detecting the error.

公开(公告)号：US20240184698A1

公开(公告)日：2024-06-06

申请号：US18341091

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook

IPC: G06F12/0817

CPC classification number: G06F12/0828 ,  G06F2212/621

Abstract: A method and apparatus for a cache coherency state request vector is described. A method includes selecting, by a first agent, one or more bits in a cache coherency state request vector, where a selected bit in the cache coherency state request vector indicates an acceptable cache coherency state for a cache block indicated in a request message, transmitting, by the first agent to a second agent, the request message for the cache block, the request message including the cache coherency state request vector, and receiving, by the first agent from the second agent, a response message with a cache coherency response state, wherein the cache coherency response state indicates a cache coherency state responsive to the cache coherency state request vector.

公开(公告)号：US20240184707A1

公开(公告)日：2024-06-06

申请号：US18341244

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Michael Klinglesmith ,  Eric Andrew Gouldey ,  Wesley Waylon Terpstra

IPC: G06F12/0891

CPC classification number: G06F12/0891

Abstract: An agent may be configured to invoke a first eviction operation that is interruptible by probe operations when receiving a first type of eviction message and invoke a second eviction operation in which probe operations are interruptible by the second eviction operation when receiving a second type of eviction message. In some implementations, the agent may maintain a data storage that is inclusive of at least one of unique or dirty cache blocks in a cache maintained by an agent that transmits the second type of eviction message. In some implementations, the agent may prevent a cache block from transitioning from a modified state to an exclusive state when the agent invokes the second eviction operation to evict the cache block. In some implementations, the agent may convert from the second eviction operation to the first eviction operation when receiving the second type of eviction message.

公开(公告)号：US20240184703A1

公开(公告)日：2024-06-06

申请号：US18341217

申请日：2023-06-26

Applicant: SiFive, Inc.

Inventor： Wesley Waylon Terpstra ,  Eric Andrew Gouldey ,  Michael Klinglesmith ,  Henry Cook

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/0815

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0815

Abstract: A method and apparatus for a speculative request indicator is described. A method includes providing, for a cache hierarchy, a messaging protocol used for transfer operations among agents in the cache hierarchy, the messaging protocol indicating acceptable cache coherency states for a cache block indicated in a request message and providing, in the messaging protocol for selection by an agent, a speculative request indicator when sending the request message, wherein the speculative request indicator differentiates between a demand request and a speculative request with respect to the cache block.

公开(公告)号：US20250147761A1

公开(公告)日：2025-05-08

申请号：US19016702

申请日：2025-01-10

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Terpstra ,  Michael Klinglesmith

IPC: G06F9/30 ,  G06F12/0862 ,  G06F12/0897

Abstract: Prefetch circuitry may be configured to transmit a message to cancel a prefetch of one or more cache blocks of a group. The message may correspond to a prefetch message by indicating an address for the group and a bit field for the one or more cache blocks of the group to cancel. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, and the message may be transmitted to the higher level cache via a lower level cache. In some implementations, the message may target a higher level cache to cancel prefetching the one or more cache blocks, the message may be transmitted to a lower level cache via a first command bus, and the lower level cache may forward the message to the higher level cache via a second command bus.