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11.发明申请Radio Frequency (RF) Receivers Having Whitened Digital Frame Processing And Related Methods 有权具有美白数字帧处理和相关方法的射频（RF）接收机公开(公告)号：US20150365117A1
公开(公告)日：2015-12-17
申请号：US14301764
申请日：2014-06-11
Applicant: Silicon Laboratories Inc.
Inventor： Michael R. May , Junsong Li
CPC classification number: H04B1/16 , H04B1/001 , H04L7/0079
Abstract: Radio frequency (RF) receivers having whitened digital frame processing and related methods are disclosed. Disclosed embodiments whiten frequency domain interference generated periodic current pulses from by digital frame processing by applying a variable time delay to the frame control signals that initiate digital frame processing. For one embodiment, the variable time delay is achieved by waiting a variable number of digital clock cycles for each digital frame processing cycle. Still further, a variable number of no operation (NO-OP) cycles can be performed at the beginning of each frame processing cycle to provide the variable time delay for the variable number of digital clock cycles. Other variable time delay techniques could also be utilized while still taking advantage of the whitened digital frame processing embodiments described herein.
Abstract translation: 公开了具有白化数字帧处理和相关方法的射频（RF）接收机。 公开的实施方案白化频域干扰通过对发起数字帧处理的帧控制信号应用可变时间延迟从数字帧处理产生周期性电流脉冲。 对于一个实施例，通过为每个数字帧处理周期等待可变数目的数字时钟周期来实现可变时间延迟。 此外，可以在每个帧处理周期的开始执行可变数目的无操作（NO-OP）周期，以为可变数量的数字时钟周期提供可变时间延迟。 还可以利用其他可变时间延迟技术，同时仍然利用本文描述的增白数字帧处理实施例。
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12.发明授权Radio frequency (RF) receivers with whitened digital clocks and related methods 有权具有白化数字时钟和相关方法的射频（RF）接收机公开(公告)号：US09042499B2
公开(公告)日：2015-05-26
申请号：US14062958
申请日：2013-10-25
Applicant: Silicon Laboratories Inc.
Inventor： Michael R. May , Scott T. Haban
CPC classification number: H04B1/12 , H04B15/06 , H04B2215/067
Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.
Abstract translation: 公开了具有白化数字时钟和相关方法的射频（RF）接收机。 公开的实施例产生具有用于操作数字处理块的随机变化的白化时钟，使得由白化时钟产生的干扰在接收的RF信号频谱内被视为白噪声。 RF输入信号由RF前端（RFFE）接收，RF前端输出与RF输入信号内的信道相关的模拟信号。 这些模拟信号被转换成数字信息并由数字接收路径电路进行处理，该电路输出与该信道相关联的数字数据。 数字接收路径电路包括白化时钟发生器，其产生具有随机变化的白化时钟，以及基于白化时钟操作的数字处理块。 此外，RFFE和数字接收路径电路位于单个集成电路内。
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13.发明申请Radio Frequency (RF) Receivers With Whitened Digital Clocks And Related Methods 有权带有美白数字时钟的射频（RF）接收机及相关方法公开(公告)号：US20150117573A1
公开(公告)日：2015-04-30
申请号：US14062958
申请日：2013-10-25
Applicant: Silicon Laboratories Inc.
Inventor： Michael R. May , Scott T. Haban
IPC: H04B1/12
CPC classification number: H04B1/12 , H04B15/06 , H04B2215/067
Abstract: Radio frequency (RF) receivers having whitened digital clocks and related methods are disclosed. Disclosed embodiments generate whitened clocks having random variations that are used to operate digital processing blocks so that interference created by the whitened clocks is seen as white noise within the received RF signal spectrum. RF input signals are received by RF front-ends (RFFEs) that output analog signals associated with channels within the RF input signals. These analog signals are converted to digital information and processed by digital receive path circuitry that outputs digital data associated with the channel. The digital receive path circuitry includes a whitened clock generator that generates a whitened clock having random variations and which a digital processing block that operates based upon the whitened clock. Further, the RFFE and the digital receive path circuitry are located within a single integrated circuit.
Abstract translation: 公开了具有白化数字时钟和相关方法的射频（RF）接收机。 公开的实施例产生具有用于操作数字处理块的随机变化的白化时钟，使得由白化时钟产生的干扰在接收的RF信号频谱内被视为白噪声。 RF输入信号由RF前端（RFFE）接收，RF前端输出与RF输入信号内的信道相关的模拟信号。 这些模拟信号被转换成数字信息并由数字接收路径电路进行处理，该电路输出与该信道相关联的数字数据。 数字接收路径电路包括白化时钟发生器，其产生具有随机变化的白化时钟，以及基于白化时钟操作的数字处理块。 此外，RFFE和数字接收路径电路位于单个集成电路内。
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公开(公告)号：US20220116250A1
公开(公告)日：2022-04-14
申请号：US17066242
申请日：2020-10-08
Applicant: Silicon Laboratories Inc.
Inventor： Carlos Jesus Briseno-Vidrios , Michael R. May , Patrick De Bakker
IPC: H04L27/06
Abstract: An integrated circuit includes a demodulator to demodulate a signal simultaneously transmitted over an isolation communication channel and obtain gate information and configuration information. The demodulator includes a gate demodulation path and a configuration demodulation path. The received signal oscillates at a first frequency to represent a first state, oscillates at different frequencies to represent a seconds state, oscillates at a third frequency (or third and fourth frequencies), which are lower than the first frequency, to represent a third state, and the received signal is steady state to represent a fourth state. The gate demodulation path detects the first and second states. The configuration demodulation path includes first and second sub-demodulation paths. An envelope detector in the first sub-demodulation path detects the second state and the second sub-demodulation path detects the third state. The configuration demodulation paths uses an output of the gate demodulation path.
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公开(公告)号：US20210255678A1
公开(公告)日：2021-08-19
申请号：US16791210
申请日：2020-02-14
Applicant: Silicon Laboratories Inc.
Inventor： Rex Tak Ying Wong , Michael R. May , Pio Balmelli
IPC: G06F1/26 , G01R19/165 , G06F13/40
Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.
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Patent Agency Ranking
公开(公告)号：US10756823B2
公开(公告)日：2020-08-25
申请号：US15975307
申请日：2018-05-09
Applicant: Silicon Laboratories Inc.
Inventor： Carlos Briseno-Vidrios , Michael R. May , Patrick J. de Bakker
Abstract: A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.
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公开(公告)号：US10699995B2
公开(公告)日：2020-06-30
申请号：US15974857
申请日：2018-05-09
Applicant: Silicon Laboratories Inc.
Inventor： Michael R. May , Charles Guo Lin , Carlos Briseno-Vidrios
IPC: H01L23/498 , H01L23/00 , H01L23/64
Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.
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公开(公告)号：US20170288764A1
公开(公告)日：2017-10-05
申请号：US15086248
申请日：2016-03-31
Applicant: Silicon Laboratories Inc.
Inventor： Russell Croman , Nebojsa Stanic , Michael Johnson , Dan B. Kasha , Michael R. May
CPC classification number: H04B7/08 , H04B1/0064 , H04B1/0075 , H04B1/16
Abstract: In an example, a method includes: in a first mode, causing a first tuner of an entertainment system to receive and process a first RF signal from a first antenna configured for a first band to output a first audio signal of a first radio station and causing a second tuner of the entertainment system to receive a second RF signal from a second antenna configured for the first band to determine signal quality metrics for one or more radio stations of the first band; in a second mode, causing the first tuner to output a first signal representation of the first RF signal and causing the second tuner to receive and process the second RF signal to output a second signal representation of the second RF signal; and causing a phase diversity combining circuit to process the first and second signal representations to output an audio signal of the first radio station, without disruption of output from the entertainment system of a broadcast of the first radio station.
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公开(公告)号：US20170093448A1
公开(公告)日：2017-03-30
申请号：US14868473
申请日：2015-09-29
Applicant: Silicon Laboratories Inc.
Inventor： Michael R. May
CPC classification number: H04B1/1036 , H03H11/0405 , H03H11/12
Abstract: In one embodiment, an integrated circuit includes: a first input pad to receive a radio frequency (RF) signal; a radio receiver to process the RF signal and output a digitally processed signal; an analog filter to receive a digital signal via an input signal path and output a drive signal via an output signal path; and a first output pad coupled to the output signal path to output a filtered digital signal based on the drive signal.
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公开(公告)号：US09124334B2
公开(公告)日：2015-09-01
申请号：US14283648
申请日：2014-05-21
Applicant: Silicon Laboratories Inc.
Inventor： Javier Elenes , Brian D. Green , Michael R. May
CPC classification number: H04B1/086 , H04H20/30 , H04H60/12 , H04H2201/18 , H04L25/03834 , H04L27/0008 , H04W52/0229 , Y02D70/00
Abstract: In one embodiment, a receiver front end circuit can receive and process multiple radio frequency (RF) signals and output downconverted signals corresponding to these signals. In turn, multiple signal processors can be coupled to this front end. Specifically, a first signal processor can receive and process the downconverted signals to output a first signal obtained from content of a first RF signal, and a second signal processor can receive and process the downconverted signals to output a second signal obtained from content of a second RF signal. In addition, the apparatus may include a detection circuit coupled to the receiver front end circuit to detect presence of at least the second signal and enable the second signal processor responsive to the detected presence.
Abstract translation: 在一个实施例中，接收器前端电路可以接收和处理多个射频（RF）信号并输出与这些信号对应的下变频信号。 反过来，多个信号处理器可以耦合到该前端。 具体地，第一信号处理器可以接收并处理下变频信号以输出从第一RF信号的内容获得的第一信号，并且第二信号处理器可以接收并处理下变频信号以输出从第二RF信号的内容获得的第二信号 射频信号。 此外，该装置可以包括耦合到接收器前端电路的检测电路，以检测至少第二信号的存在，并使第二信号处理器能够响应于检测到的存在。
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