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公开(公告)号：US20200226062A1
公开(公告)日：2020-07-16
申请号：US16833680
申请日：2020-03-30
Applicant: Silicon Motion, Inc.
Inventor： HONG-JUNG HSU , Chun-Chieh Kuo
Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.
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公开(公告)号：US20170308318A1
公开(公告)日：2017-10-26
申请号：US15643501
申请日：2017-07-07
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7206 , G11C11/5628 , G11C11/5642 , Y02D10/13
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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13.发明申请公开(公告)号：US20130107625A1
公开(公告)日：2013-05-02
申请号：US13658086
申请日：2012-10-23
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Ching-Hui Lin , Yang-Chih Shen , Chun-Chieh Kuo
CPC classification number: G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641
Abstract: The invention provides a flash memory apparatus. In one embodiment, the flash memory apparatus comprises a flash memory and a flash memory controller. The flash memory comprises a write circuit and a memory cell array comprising a plurality of memory cells, wherein the write circuit is coupled to the memory cell array to write data in the memory cells. The flash memory controller is coupled to the write circuit, obtains a total capacity and a used data amount of the flash memory, and directs the write circuit to perform data writing in a one-bit mode when a ratio of the user data amount to the total capacity is less than a first predetermined value.
Abstract translation: 本发明提供一种闪存装置。 在一个实施例中，闪存装置包括闪速存储器和闪存控制器。 闪速存储器包括写电路和包括多个存储单元的存储单元阵列，其中写电路耦合到存储单元阵列以将数据写入存储单元。 闪速存储器控制器耦合到写入电路，获得闪存的总容量和使用的数据量，并且当用户数据量与存储器的比率相对应时，引导写入电路以一位模式执行数据写入 总容量小于第一预定值。
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公开(公告)号：US20210271402A1
公开(公告)日：2021-09-02
申请号：US17324121
申请日：2021-05-19
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US10824354B2
公开(公告)日：2020-11-03
申请号：US16686200
申请日：2019-11-17
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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Patent Agency Ranking
公开(公告)号：US10657048B2
公开(公告)日：2020-05-19
申请号：US15783953
申请日：2017-10-13
Applicant: Silicon Motion, Inc.
Inventor： Hong-Jung Hsu , Chun-Chieh Kuo
Abstract: A garbage collection method for a data storage device includes steps of: entering a background mode from a foreground mode; selecting a plurality of source data blocks from a plurality of in-use data blocks; dividing a mapping table into a plurality of sub-mapping tables and selecting one of the sub-mapping tables as a target sub-mapping table, wherein the target sub-mapping table is used to manage one of the source data blocks; selecting a destination data block from a plurality of spare data blocks; and sequentially updating a correspondence relationship of data stored in the target sub-mapping table from the source data blocks to the destination data block, wherein the updating comprises copying the data stored in the source data blocks to the destination data block.
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公开(公告)号：US10521142B2
公开(公告)日：2019-12-31
申请号：US16260142
申请日：2019-01-29
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US20190155531A1
公开(公告)日：2019-05-23
申请号：US16260142
申请日：2019-01-29
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7206 , G11C11/5628 , G11C11/5642 , Y02D10/13
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US09256529B2
公开(公告)日：2016-02-09
申请号：US14596236
申请日：2015-01-14
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7206 , G11C11/5628 , G11C11/5642 , Y02D10/13
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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公开(公告)号：US20240152288A1
公开(公告)日：2024-05-09
申请号：US18412635
申请日：2024-01-15
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G11C11/5628 , G11C11/5642 , G06F2212/7201 , G06F2212/7206 , Y02D10/00
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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