公开(公告)号：US11687432B2

公开(公告)日：2023-06-27

申请号：US17149663

申请日：2021-01-14

Applicant: Silicon Motion, Inc.

Inventor： Chun-Cheng Lee ,  Che-Min Lin ,  Kuan-Chun Yu ,  Sheng-I Hsu

IPC: G06F11/30 ,  G06F13/16 ,  G06F11/00 ,  G06F12/02 ,  G06F11/07

CPC classification number: G06F11/3058 ,  G06F11/002 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0238 ,  G06F13/1668

Abstract: A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.

公开(公告)号：US20220222160A1

公开(公告)日：2022-07-14

申请号：US17149663

申请日：2021-01-14

Applicant: Silicon Motion, Inc.

Inventor： Chun-Cheng Lee ,  Che-Min Lin ,  Kuan-Chun Yu ,  Sheng-I Hsu

IPC: G06F11/30 ,  G06F11/07 ,  G06F11/00 ,  G06F12/02 ,  G06F13/16

Abstract: A data accessing method using dynamic speed adjustment with aid of a thermal control unit, and associated apparatus such as memory device, memory controller, etc. are provided. The data accessing method includes: utilizing a thermal control unit to start monitoring temperature at a predetermined intra-controller location of the memory controller; in response to at least one accessing request from a host device, controlling a transmission interface circuit to perform data transmission between the host device and the memory controller at an original communications speed, for accessing data in the NV memory; in response to the temperature being greater than a first temperature threshold, detecting an increment of the temperature between a first start time point and a first end time point; based on at least one first predetermined rule, determining a first communications speed according to the increment; and switching from the original communications speed to the first communications speed.

公开(公告)号：US11366674B2

公开(公告)日：2022-06-21

申请号：US16732338

申请日：2020-01-01

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu

IPC: G06F9/445 ,  G06F9/451 ,  G06F12/02 ,  G11C11/406 ,  G06F13/16 ,  G06F11/30

Abstract: A method for performing dynamic throttling control with aid of configuration setting and associated apparatus such as a host device, a data storage device and a controller thereof are provided. The method includes: utilizing the host device to provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device; and in response to the selection of said any of the plurality of throttling control configurations by the user, utilizing the host device to send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.

公开(公告)号：US11199991B2

公开(公告)日：2021-12-14

申请号：US16712160

申请日：2019-12-12

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu

IPC: G06F3/06

Abstract: The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.

公开(公告)号：US10992322B2

公开(公告)日：2021-04-27

申请号：US16745255

申请日：2020-01-16

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: H03M13/29 ,  H03M13/09 ,  H03M13/13 ,  G06F11/10 ,  G06F11/00 ,  H03M13/00 ,  G06F12/02

Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.

公开(公告)号：US10552262B2

公开(公告)日：2020-02-04

申请号：US15948586

申请日：2018-04-09

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F3/06 ,  G11C29/04

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, is disclosed to include at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

公开(公告)号：US10469105B2

公开(公告)日：2019-11-05

申请号：US15260330

申请日：2016-09-09

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Sheng-I Hsu

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/02 ,  H03M13/09 ,  H03M13/29 ,  H03M13/13

Abstract: A data storage system includes: a processing circuit arranged to receive a data bytes from a host; a calculating circuit arranged to generate a cyclic redundancy check code according to a logical block address, and combine the cyclic redundancy check code and the data bytes to be a data sector; and an encoding circuit arranged to encode the data sector to generate an error checking and correcting code, and combine the data sector and the error checking and correcting code to be a storing data.

公开(公告)号：US20180329816A1

公开(公告)日：2018-11-15

申请号：US15853210

申请日：2017-12-22

Applicant: Silicon Motion, Inc.

Inventor： Sheng-I Hsu

IPC: G06F12/02 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1004 ,  G06F11/1068 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7204

Abstract: A data storage device includes a flash memory, a data processing module and a flash memory controller. Corresponding to the operation of a host, the flash memory controller arranges the flash memory to store data, and it stores a mapping table to record the mapping information between the flash memory and the logical address of the host. When the host transmits a trim command to invalidate a specific portion of the mapping table and the host manages to read the data of the specific portion, the flash memory controller sets up a flag to be open so that the data is transmitted to the host without the implement of the data processing module.

公开(公告)号：US09977714B2

公开(公告)日：2018-05-22

申请号：US14331575

申请日：2014-07-15

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang ,  Yang-Chih Shen ,  Sheng-I Hsu

IPC: G06F11/00 ,  G06F11/10 ,  G06F12/02 ,  G06F3/06 ,  G11C29/04

CPC classification number: G06F11/108 ,  G06F3/06 ,  G06F12/0246 ,  G11C2029/0411

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by an arbiter, includes at least the following steps. After transmitting data to first storage units each connected to one of storage-unit access interfaces in a first batch, the arbiter issues a data write command to each first storage unit, thereby enabling each first storage unit to start a physical data programming. During the physical data programming of each first storage unit, data is transmitted to second storage units each connected to one of the storage-unit access interfaces in a second batch.

公开(公告)号：US12160239B2

公开(公告)日：2024-12-03

申请号：US18498054

申请日：2023-10-31

Applicant: Silicon Motion, Inc.

Inventor： Tien-Hsing Yao ,  Chun-Cheng Lee ,  Sheng-I Hsu

IPC: H03K21/02 ,  G06F1/3234 ,  H03K5/00 ,  H03K21/08 ,  H03K21/10 ,  H03K21/40

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.