公开(公告)号：US11444091B2

公开(公告)日：2022-09-13

申请号：US17129865

申请日：2020-12-21

Applicant: Silicon Storage Technology, Inc.

Inventor： Jack Sun ,  Chunming Wang ,  Xian Liu ,  Andy Yang ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: H01L21/00 ,  H01L27/11531 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11529

Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.

公开(公告)号：US11315635B2

公开(公告)日：2022-04-26

申请号：US17152696

申请日：2021-01-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: G11C16/04 ,  G11C16/16 ,  H01L27/11556 ,  H01L27/11521 ,  H01L29/423

Abstract: A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.

公开(公告)号：US10833179B2

公开(公告)日：2020-11-10

申请号：US16576389

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20200013882A1

公开(公告)日：2020-01-09

申请号：US16576348

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L21/3213 ,  H01L27/11521 ,  H01L27/11536 ,  H01L27/11531 ,  H01L29/423 ,  H01L49/02

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20190214396A1

公开(公告)日：2019-07-11

申请号：US16160812

申请日：2018-10-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

IPC: H01L27/11521

Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

公开(公告)号：US20230292504A1

公开(公告)日：2023-09-14

申请号：US17834746

申请日：2022-06-07

Applicant: Silicon Storage Technology, Inc.

Inventor： Zhuoqiang Jia ,  Leo Xing ,  Xian Liu ,  Serguei Jourba ,  Nhan Do

IPC: H01L27/11531 ,  H01L29/423 ,  H01L21/28 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11531 ,  H01L29/42328 ,  H01L29/40114 ,  H01L29/7883 ,  H01L29/66825

Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.

公开(公告)号：US11316024B2

公开(公告)日：2022-04-26

申请号：US17165934

申请日：2021-02-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: G11C11/34 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

公开(公告)号：US20220093623A1

公开(公告)日：2022-03-24

申请号：US17151944

申请日：2021-01-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Guo Xiang Song ,  Leo Xing ,  Jack Sun ,  Xian Liu ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66

Abstract: A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.

公开(公告)号：US11081553B2

公开(公告)日：2021-08-03

申请号：US16868143

申请日：2020-05-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Chunming Wang ,  Guo Yong Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L21/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788

Abstract: A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

公开(公告)号：US20210005724A1

公开(公告)日：2021-01-07

申请号：US16796412

申请日：2020-02-20

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Nhan Do ,  Leo Xing ,  Guo Yong Liu ,  Melvin Diao

IPC: H01L21/28 ,  H01L27/11521

Abstract: A method of forming a memory device that includes forming a first polysilicon layer using a first polysilicon deposition over a semiconductor substrate, forming an insulation spacer on the first polysilicon layer, and removing some of the first polysilicon layer to leave a first polysilicon block under the insulation spacer. A source region is formed in the substrate adjacent a first side surface of the first polysilicon block. A second polysilicon layer is formed using a second polysilicon deposition. The second polysilicon layer is partially removed to leave a second polysilicon block over the substrate and adjacent to a second side surface of the first polysilicon block. A third polysilicon layer is formed using a third polysilicon deposition. The third polysilicon layer is partially removed to leave a third polysilicon block over the source region. A drain region is formed in the substrate adjacent to the second polysilicon block.