公开(公告)号：US10600708B2

公开(公告)日：2020-03-24

申请号：US16170904

申请日：2018-10-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Shan Tsai ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.

公开(公告)号：US20190057917A1

公开(公告)日：2019-02-21

申请号：US15860222

申请日：2018-01-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Shan Tsai ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: An electronic package and a method of fabricating the same are provided. The method includes disposing an electronic component on a first side of an interposer, forming a first encapsulant on the first side of the interposer to encapsulate the electronic component, forming a plurality of conductive elements on a second side of the interposer, and forming a second encapsulant on the second side of the interposer to encapsulate the conductive elements. During thermal cycling of the electronic package, shrinkage forces of the first encapsulant and the second encapsulant can offset each other so as to mitigate warping of the interposer.

公开(公告)号：US20210320076A1

公开(公告)日：2021-10-14

申请号：US16922169

申请日：2020-07-07

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Yuan-Hung Hsu

IPC: H01L23/00

Abstract: Provided is an electronic package, including a first substrate of a first conductive structure and a second substrate of a second conductive structure, where a first conductive layer, a bump body and a metal auxiliary layer of the first conductive structure are sequentially formed on the first substrate, and a metal pillar, a second conductive layer, a metal layer and a solder layer of the second conductive structure are sequentially formed on the second substrate, such that the solder layer is combined with the bump body and the metal auxiliary layer to stack the first substrate and the second substrate. Therefore, the arrangement of the bump body and the metal auxiliary layer allows complete reaction of the IMCs after reflowing the solder layer, and the volume of the conductive structures will not continue to shrink. As such, the problem of cracking of the conductive structures can be effectively averted.

公开(公告)号：US20210280530A1

公开(公告)日：2021-09-09

申请号：US16876460

申请日：2020-05-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Jen Chen ,  Chih-Hsun Hsu ,  Chee-Key Chung ,  Jia-Wei Pan ,  Chang-Fu Lin

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.

公开(公告)号：US20210082837A1

公开(公告)日：2021-03-18

申请号：US16867937

申请日：2020-05-06

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Yuan-Hung Hsu ,  Chi-Jen Chen

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768

Abstract: An electronic package is provided and includes a plurality of electronic elements, a spacing structure connecting each of the plurality of electronic elements, and a plurality of conductive elements electrically connected to the plurality of electronic elements and serving as external contacts. The spacing structure has a recess to enhance the flexibility of the electronic elements after the electronic elements are connected to one another, thereby preventing the problem of warpage. A method for fabricating the electronic package is also provided.

公开(公告)号：US20210068260A1

公开(公告)日：2021-03-04

申请号：US17086888

申请日：2020-11-02

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Lung Huang ,  Chee-Key Chung ,  Chang-Fu Lin ,  Yuan-Hung Hsu

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K3/30

Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.

公开(公告)号：US20190252344A1

公开(公告)日：2019-08-15

申请号：US15980255

申请日：2018-05-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Min Lo ,  Chee-Key Chung ,  Chang-Fu Lin ,  Kuo-Hua Yu ,  Hsiang-Hua Huang

IPC: H01L23/00 ,  H01L21/48

Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.

公开(公告)号：US10354891B2

公开(公告)日：2019-07-16

申请号：US15945308

申请日：2018-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chih-Jen Yang ,  Yu-Chih Cheng ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/52 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

公开(公告)号：US20190181021A1

公开(公告)日：2019-06-13

申请号：US15945308

申请日：2018-04-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Po-Hao Wang ,  Chih-Jen Yang ,  Yu-Chih Cheng ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/568 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/06 ,  H01L2224/04105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3512

Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.

公开(公告)号：US20190164861A1

公开(公告)日：2019-05-30

申请号：US16170904

申请日：2018-10-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Shan Tsai ,  Chee-Key Chung ,  Chang-Fu Lin

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.