公开(公告)号：US20240332300A1

公开(公告)日：2024-10-03

申请号：US18744087

申请日：2024-06-14

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Hirotaka TAKENO ,  Atsushi OKAMOTO

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US20220231681A1

公开(公告)日：2022-07-21

申请号：US17577701

申请日：2022-01-18

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Junji IWAHORI

IPC: H03K17/16

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US20220231054A1

公开(公告)日：2022-07-21

申请号：US17714683

申请日：2022-04-06

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US20210210466A1

公开(公告)日：2021-07-08

申请号：US17206257

申请日：2021-03-19

Applicant: SOCIONEXT INC.

Inventor： Atsushi OKAMOTO ,  Hirotaka TAKENO ,  Wenzhen WANG

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/50 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US20250006635A1

公开(公告)日：2025-01-02

申请号：US18886493

申请日：2024-09-16

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20240274536A1

公开(公告)日：2024-08-15

申请号：US18432890

申请日：2024-02-05

Applicant: SOCIONEXT INC.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L27/0922 ,  H01L27/0924

Abstract: A semiconductor device includes: a substrate; a circuit region provided on the substrate; a first power supply line and a second power supply line, positioned in the circuit region; a first fin and a second fin, each extending in a first direction in the circuit region, in plan view, and protruding from the substrate; a first power supply switching circuit, positioned in the circuit region and including a first transistor formed with the first fin, the first circuit electrically connecting the first and second power supply lines, and the first fin extending in the first power supply switching circuit without cutting; and a second power supply switching circuit, positioned in the circuit region and including a second transistor formed with the second fin, the second circuit electrically connecting the first and second power supply lines, and including a fin-cut part in which the second fin is cut.

公开(公告)号：US20240224492A1

公开(公告)日：2024-07-04

申请号：US18606421

申请日：2024-03-15

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Wenzhen WANG ,  Hirotaka TAKENO

IPC: H10B10/00

CPC classification number: H10B10/18

Abstract: A semiconductor device includes first and second power supply lines and first and second ground lines provided on a first surface of a substrate, and third and fourth power supply lines provided on a second surface of the substrate. The second power supply line and the third power supply line are connected through vias provided in the substrate. The semiconductor device includes first and second areas arranged to have a third area sandwiched in-between, and a power switch circuit including switch transistors connected between the third and fourth power supply lines.

公开(公告)号：US20220293634A1

公开(公告)日：2022-09-15

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

公开(公告)号：US20220230954A1

公开(公告)日：2022-07-21

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen WANG ,  Atsushi OKAMOTO ,  Hirotaka TAKENO

IPC: H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US20210210468A1

公开(公告)日：2021-07-08

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka TAKENO ,  Wenzhen WANG ,  Atsushi OKAMOTO

IPC: H01L25/065 ,  H01L27/02

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.