公开(公告)号：US12184282B2

公开(公告)日：2024-12-31

申请号：US17724247

申请日：2022-04-19

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto ,  Wenzhen Wang

IPC: H03K19/173 ,  H01L23/495 ,  H01L23/528 ,  H01L29/78

Abstract: A semiconductor device has: a first chip having a substrate and a first wiring layer; and a second wiring layer formed on a second surface of the substrate. The second wiring layer has a first power supply line, and a second power supply line. The first chip has a first ground line, a third power supply line, a fourth power supply line, vias formed in the substrate and connecting the first power supply line and the third power supply line, a first area in which the first ground line and the fourth power supply line are arranged, and a first circuit connected between the first ground line and the third power supply line. A switch is connected between the first power supply line and the second power supply line. In a plan view, the third power supply line, the vias, and the first circuit are arranged in the first area.

公开(公告)号：US12154904B2

公开(公告)日：2024-11-26

申请号：US17714683

申请日：2022-04-06

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Wenzhen Wang ,  Hirotaka Takeno

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first interconnection layer formed on a first surface of the substrate; and a second interconnection layer formed on a second surface opposite to the first surface of the substrate. The second interconnection layer includes a first power line to which a first power potential is applied, a second power line to which a second power potential is applied, and a first switch connected between the first power line and the second power line. The first chip includes a first grounding line, a third power line to which the second power potential is applied, and a first region in which the first grounding line and the third power line are disposed. In plan view, the first switch overlaps the first region.

公开(公告)号：US11626386B2

公开(公告)日：2023-04-11

申请号：US17206257

申请日：2021-03-19

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L23/50 ,  H01L25/065 ,  H01L23/538 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US10797042B2

公开(公告)日：2020-10-06

申请号：US16438026

申请日：2019-06-11

Applicant: SOCIONEXT INC.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US12068288B2

公开(公告)日：2024-08-20

申请号：US18179013

申请日：2023-03-06

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L23/50 ,  H01L23/538 ,  H01L25/065 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5384 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.

公开(公告)号：US11233044B2

公开(公告)日：2022-01-25

申请号：US17014662

申请日：2020-09-08

Applicant: SOCIONEXT INC.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L23/528 ,  H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes a semiconductor substrate, a first standard cell including a first active region and a second active region, and a power switching circuit including a first switching transistor electrically connected between a first interconnect and a second interconnect over the semiconductor substrate, and including a first buffer connected to a gate of the first switching transistor, the first buffer including a third active region and a fourth active region, and wherein the first buffer adjoins, in a plan view, the first standard cell in a first direction, wherein an arrangement of the first active region matches an arrangement of the third active region in a second direction different from the first direction, and wherein an arrangement of the second active region matches an arrangement of the fourth active region in the second direction.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US12087735B2

公开(公告)日：2024-09-10

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka Takeno ,  Wenzhen Wang ,  Atsushi Okamoto

IPC: H01L25/065 ,  G11C5/14 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L27/0207 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US12046598B2

公开(公告)日：2024-07-23

申请号：US17507567

申请日：2021-10-21

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US20220293634A1

公开(公告)日：2022-09-15

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi OKAMOTO ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L27/118

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.