公开(公告)号：US06181617B2

公开(公告)日：2001-01-30

申请号：US09483549

申请日：2000-01-14

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6011731A

公开(公告)日：2000-01-04

申请号：US259221

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US5974577A

公开(公告)日：1999-10-26

申请号：US949419

申请日：1997-10-14

申请人： Manny K. Ma

发明人： Manny K. Ma

IPC分类号： G01R19/165 ,  G01R31/28

CPC分类号： G01R19/165 ,  G01R31/2884

摘要： An integrated circuit package having external pins includes a function circuit, such as an address buffer, receiving an input voltage through one of the pins. If the input voltage exceeds a maximum rated voltage, the function circuit can be damaged by voltage over-stress. To provide a definitive indication that the function circuit may have been over-stressed, a diode and a fuse are connected in series between the function circuit's pin and ground. When the input voltage nears the maximum rated voltage, the diode biases and applies a voltage to the fuise. The fuse is selected so that when the input voltage exceeds the maximum rated voltage, the applied voltage blows the fuse. At a later time, the function circuit can be tested for over-stress by applying a voltage to the function circuit's pin which is sufficient to forward bias the diode. If no current flows after a sufficient biasing voltage is applied to the pin, it is a definitive indication that the function circuit may have been over-stressed.

摘要翻译： 具有外部引脚的集成电路封装包括诸如地址缓冲器的功能电路，通过其中一个引脚接收输入电压。 如果输入电压超过最大额定电压，则功能电路可能因电压过压而损坏。 为了提供功能电路可能被过应力的确定指示，二极管和保险丝串联在功能电路的引脚和地之间。 当输入电压接近最大额定电压时，二极管偏置并向电源施加电压。 保险丝被选中，使得当输入电压超过最大额定电压时，施加的电压使保险丝熔断。 在稍后的时间，可以通过向功能电路的引脚施加足以使二极管正向偏置的电压来对功能电路进行过压测试。 如果在引脚施加足够的偏置电压之后没有电流流动，则功能电路可能已经过度应力的确定指示。

公开(公告)号：US06778452B2

公开(公告)日：2004-08-17

申请号：US10608060

申请日：2003-06-27

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06469944B2

公开(公告)日：2002-10-22

申请号：US09735119

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US06445629B1

公开(公告)日：2002-09-03

申请号：US09735330

申请日：2000-12-11

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C700

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US06320781B1

公开(公告)日：2001-11-20

申请号：US09824363

申请日：2001-04-02

申请人： Wen Li ,  Manny K. Ma

发明人： Wen Li ,  Manny K. Ma

IPC分类号： G11C506

CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/1048

摘要： The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.

摘要翻译： 本公开包括对存储器设备中的数据线有用的扭曲架构。 该体系结构涉及四条数据线的扭转以产生四个部分，使得每个数据线在四个部分的每一个中占据不同的位置。 具体地说，在第一部分中，第一数据线与第二数据线相邻，第二数据线与第三数据线相邻，第三数据线与第四数据线相邻; 在第二部分中，第三数据线与第一数据线相邻，第一数据线与第四数据线相邻，第四数据线与第二数据线相邻; 在第三部分中，第四数据线与第三数据线相邻，第三数据线与第二数据线相邻，第二数据线与第一数据线相邻; 并且在第四部分中，第二数据线与第四数据线相邻，第四数据线与第一数据线相邻，并且第一数据线与第三数据线相邻。 这种架构减少了数据线之间的不必要的寄生电容耦合，从而提高了速度。

公开(公告)号：US06259621B1

公开(公告)日：2001-07-10

申请号：US09610760

申请日：2000-07-06

申请人： Wen Li ,  Manny K. Ma

发明人： Wen Li ,  Manny K. Ma

IPC分类号： G11C506

CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/1048

摘要： The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.

摘要翻译： 本公开包括对存储器设备中的数据线有用的扭曲架构。 该体系结构涉及四条数据线的扭转以产生四个部分，使得每个数据线在四个部分的每一个中占据不同的位置。 具体地说，在第一部分中，第一数据线与第二数据线相邻，第二数据线与第三数据线相邻，第三数据线与第四数据线相邻; 在第二部分中，第三数据线与第一数据线相邻，第一数据线与第四数据线相邻，第四数据线与第二数据线相邻; 在第三部分中，第四数据线与第三数据线相邻，第三数据线与第二数据线相邻，第二数据线与第一数据线相邻; 并且在第四部分中，第二数据线与第四数据线相邻，第四数据线与第一数据线相邻，并且第一数据线与第三数据线相邻。 这种架构减少了数据线之间的不必要的寄生电容耦合，从而提高了速度。

公开(公告)号：US6028799A

公开(公告)日：2000-02-22

申请号：US260232

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56 ,  G11C29/00

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US5982687A

公开(公告)日：1999-11-09

申请号：US260236

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。