利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

310 条记录 (耗时 0.036 秒)

    Apparatus for minimization of data line coupling in a semiconductor memory device
    1.
    发明授权
    Apparatus for minimization of data line coupling in a semiconductor memory device 有权
    用于使半导体存储器件中的数据线耦合最小化的装置

    公开(公告)号：US06320781B1

    公开(公告)日：2001-11-20

    申请号：US09824363

    申请日：2001-04-02

    申请人： Wen Li ,  Manny K. Ma

    发明人： Wen Li ,  Manny K. Ma

    IPC分类号： G11C506

    CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/1048

    摘要： The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.

    摘要翻译： 本公开包括对存储器设备中的数据线有用的扭曲架构。 该体系结构涉及四条数据线的扭转以产生四个部分，使得每个数据线在四个部分的每一个中占据不同的位置。 具体地说，在第一部分中，第一数据线与第二数据线相邻，第二数据线与第三数据线相邻，第三数据线与第四数据线相邻; 在第二部分中，第三数据线与第一数据线相邻，第一数据线与第四数据线相邻，第四数据线与第二数据线相邻; 在第三部分中，第四数据线与第三数据线相邻，第三数据线与第二数据线相邻，第二数据线与第一数据线相邻; 并且在第四部分中，第二数据线与第四数据线相邻，第四数据线与第一数据线相邻，并且第一数据线与第三数据线相邻。 这种架构减少了数据线之间的不必要的寄生电容耦合，从而提高了速度。

    Method and apparatus for minimization of data line coupling in a semiconductor memory device
    2.
    发明授权
    Method and apparatus for minimization of data line coupling in a semiconductor memory device 有权
    用于最小化半导体存储器件中的数据线耦合的方法和装置

    公开(公告)号：US06259621B1

    公开(公告)日：2001-07-10

    申请号：US09610760

    申请日：2000-07-06

    申请人： Wen Li ,  Manny K. Ma

    发明人： Wen Li ,  Manny K. Ma

    IPC分类号： G11C506

    CPC分类号： G11C7/18 ,  G11C5/063 ,  G11C7/1048

    摘要： The present disclosure includes a twist architecture useful for the data lines in a memory device. The architecture involves the twisting of four data lines to create four portions such that each data line occupies a different position in each of the four portions. Specifically, in the first portion, the first data line is adjacent to the second data line, the second data line is adjacent to the third data line, and the third data line is adjacent to the fourth data line; in the second portion, the third data line is adjacent to the first data line, the first data line is adjacent to the fourth data line, and the fourth data line is adjacent to the second data line; in the third portion, the fourth data line is adjacent to the third data line, the third data line is adjacent to the second data line, and the second data line is adjacent to the first data line; and in the fourth portion, the second data line is adjacent to the fourth data line, the fourth data line is adjacent to the first data line, and the first data line is adjacent to the third data line. Such an architecture reduces unwanted parasitic capacitive coupling between the data lines and hence improves speed.

    摘要翻译： 本公开包括对存储器设备中的数据线有用的扭曲架构。 该体系结构涉及四条数据线的扭转以产生四个部分，使得每个数据线在四个部分的每一个中占据不同的位置。 具体地说，在第一部分中，第一数据线与第二数据线相邻，第二数据线与第三数据线相邻，第三数据线与第四数据线相邻; 在第二部分中，第三数据线与第一数据线相邻，第一数据线与第四数据线相邻，第四数据线与第二数据线相邻; 在第三部分中，第四数据线与第三数据线相邻，第三数据线与第二数据线相邻，第二数据线与第一数据线相邻; 并且在第四部分中，第二数据线与第四数据线相邻，第四数据线与第一数据线相邻，并且第一数据线与第三数据线相邻。 这种架构减少了数据线之间的不必要的寄生电容耦合，从而提高了速度。

    Metal hydrides with embedded metal structures for hydrogen storage
    3.
    发明授权
    Metal hydrides with embedded metal structures for hydrogen storage 有权
    具有嵌入金属结构的金属氢化物用于储氢

    公开(公告)号：US09506603B2

    公开(公告)日：2016-11-29

    申请号：US13615988

    申请日：2012-09-14

    申请人： Wen Li ,  John J. Vajo ,  Alan J. Jacobsen ,  Mei Cai ,  Martin P. Sulic

    发明人： Wen Li ,  John J. Vajo ,  Alan J. Jacobsen ,  Mei Cai ,  Martin P. Sulic

    IPC分类号： F17C11/00

    CPC分类号： F17C11/005 ,  Y02E60/321 ,  Y10T29/49826

    摘要： One illustrative embodiment includes materials and devices including an integrated hydrogen storage structure including a plurality of continuously connected thermally conductive elongated members, the elongated members including continuously connected openings between the elongated members; and, a metal hydride material contacting the elongated members and disposed within the connected openings and surrounding the elongated members.

    摘要翻译： 一个说明性实施例包括包括包括多个连续连接的导热细长构件的集成氢存储结构的材料和装置，细长构件包括在细长构件之间的连续连接的开口; 以及金属氢化物材料，其与细长构件接触并且设置在连接的开口内并围绕细长构件。

    Driver Integrated Circuit
    6.
    发明申请
    Driver Integrated Circuit 有权
    驱动器集成电路

    公开(公告)号：US20140125398A1

    公开(公告)日：2014-05-08

    申请号：US14122623

    申请日：2012-05-24

    申请人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

    发明人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/0175 ,  H01L2224/48137 ,  H01L2924/181 ,  H03F1/52 ,  H03F3/195 ,  H03F3/211 ,  H03F3/3022 ,  H03F2200/189 ,  H03K19/017509 ,  H01L2924/00012

    摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).

    摘要翻译： 提供可以输出超过工艺耐压的电压并满足所需设备性能（高速和高电压）的驱动器集成电路的结构。 差分输入电路，电平移位电路和输出电路通过相同的工艺制造并且被分配和布置在具有不同衬底电位（子电位）的三个或更多个芯片上。 通过对芯片的基板设置不同的施加电压，可以提供大于工艺耐受电压的输出电压（参见图2）。

    Instruction length based cracking for instruction of variable length storage operands
    7.
    发明授权
    Instruction length based cracking for instruction of variable length storage operands 有权
    指令长度为可变长度存储操作数指令的破解

    公开(公告)号：US08495341B2

    公开(公告)日：2013-07-23

    申请号：US12707163

    申请日：2010-02-17

    申请人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

    发明人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

    IPC分类号： G06F9/30

    CPC分类号： G06F9/30032 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017

    摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.

    摘要翻译： 一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。 接收至少一个可变操作数长度指令。 分析至少一个可变操作数长度指令。 基于分析来识别可变操作数长度指令中的至少一个操作数的长度。 所述至少一个可变操作数长度指令被组织成一组操作单元。 执行操作单元的集合。 所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

    PHOTODIODE ARRAYS AND METHODS OF FABRICATION
    8.
    发明申请
    PHOTODIODE ARRAYS AND METHODS OF FABRICATION 审中-公开
    光电子阵列和制造方法

    公开(公告)号：US20130168796A1

    公开(公告)日：2013-07-04

    申请号：US13343146

    申请日：2012-01-04

    申请人： Abdelaziz Ikhlef ,  Wen Li

    发明人： Abdelaziz Ikhlef ,  Wen Li

    IPC分类号： H01L27/146 ,  H01L31/18

    CPC分类号： H01L27/14658 ,  A61B6/032 ,  A61B6/037 ,  A61B6/4233 ,  H01L23/481 ,  H01L27/1446 ,  H01L27/14636 ,  H01L27/14663 ,  H01L31/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

    摘要： Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface. The photodiode array also includes a plurality of refilled conductive vias through the silicon wafer, wherein the refilled conductive vias have a doping type different than the doping type of the substrate, and an interface between the refilled conductive vias and the substrate form diode junctions. The photodiode array further includes a patterned doped layer on the first surface overlapping the refilled conductive vias, wherein the patterned doped layer defines an array of photodiodes.

    摘要翻译： 提供了光电二极管阵列和制造方法。 一个光电二极管阵列包括具有第一表面和相对的第二表面的硅晶片。 光电二极管阵列还包括通过硅晶片的多个重新填充的导电通孔，其中重新填充的导电通孔具有不同于衬底的掺杂类型的掺杂类型，并且再填充的导电通孔和衬底之间的界面形成二极管结。 光电二极管阵列还包括在重新填充的导电通孔上的第一表面上的图案化掺杂层，其中图案化掺杂层限定光电二极管阵列。

    Method and apparatus for inspecting defects of semiconductor device
    10.
    发明授权
    Method and apparatus for inspecting defects of semiconductor device 失效
    用于检查半导体器件缺陷的方法和装置

    公开(公告)号：US08385627B2

    公开(公告)日：2013-02-26

    申请号：US11500979

    申请日：2006-08-09

    申请人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

    发明人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

    IPC分类号： G06K9/00 ,  G06K7/10 ,  G01B5/28 ,  G06F11/30 ,  H04N3/14 ,  G01N21/00

    CPC分类号： G06T7/0004 ,  G06T2207/30148

    摘要： When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

    摘要翻译： 当半导体装置的检查装置重复执行规定区域数据的计算时，例如用于检测缺陷的图像处理，命令，数据加载，计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外，当通过大容量图像处理系统执行并行计算以处理微小图像时，需要许多处理器，导致成本增加。 为了解决上述问题，在本发明中，半导体装置的检查装置包括数据存储器，该数据存储器包括能够同时读写的访问部分，多个数值计算单元，连接器 数据存储器和数值计算单元，用于共同控制多个数值计算单元的处理内容的控制器，用于连接数值计算单元和控制器的另一连接器，以及用于控制数值计算之间的数据传送的数据传输控制器 单位。