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公开(公告)号：US07132856B2
公开(公告)日：2006-11-07
申请号：US10924906
申请日：2004-08-25
IPC分类号： H03K19/0175 , H03K19/096 , H03K3/017 , H03K3/356
CPC分类号： H03K3/356156
摘要： A logic circuit performs an internal level conversion function by driving portions of the circuit with different supply voltages. In one embodiment, first and second stage storage circuits are driven with different supply voltages. In another embodiment, first and second stage storage circuits are driven with a first supply voltage and an inverter coupled to the first stage storage circuit is driven with a second supply voltage. In either case, data transfer into the storage circuits may be controlled by different states of a clock signal. The logic circuit may be a flip-flop circuit, a latch circuit, or another type of circuit.
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12.发明授权公开(公告)号：US06707708B1
公开(公告)日：2004-03-16
申请号：US10241791
申请日：2002-09-10
IPC分类号： G11C1100
CPC分类号： G11C11/412 , G11C11/419
摘要： An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.
摘要翻译： 用于静态随机存取存储器的八单元，存储单元包括用于存储信息位的交叉耦合反相器，连接到局部位线的两个存取nMOSFET以访问所存储的信息位，以及两个nMOSFET，每个具有连接到地的栅极和 耦合到本地位线和交叉耦合的反相器，使得到达和从本地位线到不被读取的存储器单元的子阈值泄漏电流被平衡。
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公开(公告)号：US06563357B1
公开(公告)日：2003-05-13
申请号：US10027905
申请日：2001-12-20
IPC分类号： H03K3356
CPC分类号： H03K3/356113 , H03K3/356156 , H03K3/356173
摘要： A level converting latch, using dual-supply voltage signals and operating with reduced charge contention, converts an input signal having a first and a second potential level into an output signal also having a first and a second potential level. The first potential level of the input and output signals are the same. The second potential level of the input and output signals are unequal.
摘要翻译： 电平转换锁存器，使用双电源电压信号并以较小的电荷争用进行操作，将具有第一和第二电位电平的输入信号转换为也具有第一和第二电位电平的输出信号。 输入和输出信号的第一个电位电平是相同的。 输入和输出信号的第二个电位电平是不相等的。
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14.发明授权公开(公告)号：US09059715B2
公开(公告)日：2015-06-16
申请号：US13997584
申请日：2011-11-14
IPC分类号： H03L5/00 , H03K19/0185 , H03K3/356
CPC分类号： H03L5/00 , H03K3/356182 , H03K19/018507
摘要： Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption.
摘要翻译： 通过中压控制争用中断实现电压电平转换的方法和系统。 电压电平移位器（VLS）可以包括电压电平移位电路，用于将输入逻辑状态从输入电压摆幅电平移位到输出电压摆幅。 VLS可以包括争用电路，争用中断器和中断控制器，以产生具有临时电压摆幅的争用中断控制。 临时电压摆幅的下限可以对应于输出电压摆幅的下限。 临时电压摆幅的上限可以对应于输入电压摆幅的上限。 可以实现VLS以实现水平移位真实和互补的逻辑状态，例如用共源共栅电压开关逻辑（CVSL）。 临时电压控制的争用中断器可能有助于在相对较小的延迟和相对较小的功率和面积消耗的情况下，在竞争中断器的基于过程的电压可靠限度内维持电压。
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公开(公告)号：US07800407B1
公开(公告)日：2010-09-21
申请号：US12492938
申请日：2009-06-26
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： To pre-charge a node to one of first and second voltage levels in response to inputs received at the corresponding voltage level, to selectively level shift the node from the first voltage level to the second voltage level when in a first voltage mode, and to maintain the node at the second voltage level when in a second voltage mode. Level shifting from first voltage level may be performed within one gate stage that may be bypassed when in the second voltage mode. The node may be discharged with no delay difference between the first and second voltage modes. Inputs may include a clock signal, which may be received at either of the first and second voltage levels without level shifting the clock signal. A circuit may be implemented with a multi-core processor system to permit selective voltage mode operation of the cores.
摘要翻译： 为了响应于在相应电压电平处接收到的输入，将节点预充电到第一和第二电压电平之一，以便当在第一电压模式下选择性地将节点从第一电压电平移位到第二电压电平，并且 当处于第二电压模式时，将节点保持在第二电压电平。 可以在一个门级内执行从第一电压电平的电平转换，当处于第二电压模式时，可能被旁路。 可以在第一和第二电压模式之间没有延迟差放电节点。 输入可以包括时钟信号，其可以在第一和第二电压电平中的任何一个处接收，而不会对时钟信号进行电平移位。 电路可以用多核处理器系统来实现，以允许芯的选择性电压模式操作。
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16.发明申请Ultra wide voltage range register file circuit using programmable triple stacking 审中-公开超宽电压范围寄存器文件电路采用可编程三重堆叠公开(公告)号：US20090168557A1
公开(公告)日：2009-07-02
申请号：US12006276
申请日：2007-12-31
IPC分类号： G11C5/14
摘要： Methods and apparatus relating to expanding the operational voltage range of data storage circuits are described. In an embodiment, low voltage data storage circuit operation is improved by driving a transistor with a control word line programmable circuit. Other embodiments are also described.
摘要翻译： 描述了扩展数据存储电路的工作电压范围的方法和装置。 在一个实施例中，通过用控制字线可编程电路驱动晶体管来提高低电压数据存储电路操作。 还描述了其它实施例。
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公开(公告)号：US06404234B1
公开(公告)日：2002-06-11
申请号：US09851917
申请日：2001-05-09
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.
摘要翻译： 多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。 当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态 相。
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18.发明申请公开(公告)号：US20130271199A1
公开(公告)日：2013-10-17
申请号：US13997584
申请日：2011-11-14
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03K3/356182 , H03K19/018507
摘要： Methods and systems to implement voltage level shifting with interim-voltage-controlled contention-interruption. A voltage level shifter (VLS) may include voltage level shift circuitry to level shift an input logical state from an input voltage swing to an output voltage swing. The VLS may include contention circuitry, a contention interrupter, and an interrupt controller to generate a contention-interrupt control having an interim voltage swing. A lower limit of the interim voltage swing may correspond to a lower limit of the output voltage swing. An upper limit of the interim voltage swing may correspond to an upper limit of the input voltage swing. The VLS may be implemented to level shift true and complimentary logical states, such as with cascode voltage switch logic (CVSL). The interim-voltage-controlled contention interrupter may help to maintain voltages within process-based voltage reliability limits of the contention interrupter, with relatively little delay, and relatively little power and area consumption.
摘要翻译： 通过中压控制争用中断实现电压电平转换的方法和系统。 电压电平移位器（VLS）可以包括电压电平移位电路，用于将输入逻辑状态从输入电压摆幅电平移位到输出电压摆幅。 VLS可以包括争用电路，争用中断器和中断控制器，以产生具有临时电压摆幅的争用中断控制。 临时电压摆幅的下限可以对应于输出电压摆幅的下限。 临时电压摆幅的上限可以对应于输入电压摆幅的上限。 可以实现VLS以实现水平移位真实和互补的逻辑状态，例如用共源共栅电压开关逻辑（CVSL）。 临时电压控制的争用中断器可能有助于在相对较小的延迟和相对较小的功率和面积消耗的情况下，在竞争中断器的基于过程的电压可靠限度内维持电压。
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19.发明授权公开(公告)号：US07209395B2
公开(公告)日：2007-04-24
申请号：US10953202
申请日：2004-09-28
CPC分类号： G11C11/413 , G11C2207/007
摘要： A device includes a number of memory cells. Each of the memory cells includes a transistor stack coupled to a bit line. A value of a charge on the bit line during an access mode represents a value of data stored in an accessed memory cell. During a non-access mode, all transistors of the transistor stack are turned off to save power. The transistors are turn off regardless of the value of the data stored in the memory cells.
摘要翻译： 一种设备包括多个存储单元。 每个存储单元包括耦合到位线的晶体管堆叠。 访问模式期间位线上的电荷值表示存储在访问存储单元中的数据的值。 在非访问模式期间，晶体管堆叠的所有晶体管都被关闭以节省功率。 无论存储在存储器单元中的数据的值如何，晶体管都截止。
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20.发明申请公开(公告)号：US20170193376A1
公开(公告)日：2017-07-06
申请号：US14989694
申请日：2016-01-06
CPC分类号： G06N5/047 , G06F16/90344 , G06N7/005 , H04L63/1416
摘要： A method and apparatus are described for performing complex regex pattern matching utilizing filters based on truncated Deterministic Finite Automata (DFA). For example, one embodiment of a method comprises: representing a set of reference strings as a DFA; truncating the DFA based on a truncating policy, wherein the truncated DFA does not generate a false positive match; creating a filter based on the truncated DFA; filtering an input string against the set of reference strings by running the input string through the filter.
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